generate with step other than unit

Altera_Forum · ‎08-26-2013

Hi,

I need to write a GENERATE statement, but the step must be different from unit.

Something like:


   gen: for i in 0 to 20 generate
      temp(i) <= temp(i+4-2)  or temp(i+4-1);
   end generate;

this "i" must be incremented by 4 units instead of 1.

Regards

Jaraqui

Altera_Forum · ‎08-26-2013

with something like this:

gen: for i in 0 to 4 generate

temp(i) <= temp(i * 4 +4-2) or temp(i * 4+4-1);

end generate;

but check the range of i.

Altera_Forum · ‎08-26-2013

--- Quote Start ---

with something like this:

gen: for i in 0 to 4 generate

temp(i) <= temp(i * 4 +4-2) or temp(i * 4+4-1);

end generate;

but check the range of i.

--- Quote End ---

thank you! I will test this solution, but I need only temp(0), temp(4), temp(8), ... be the positions to receive assignments.

Writing in this way, I suspect that temp(0), temp(1), temp(2), ... would receive assignments

Regards

Jaraqui

Altera_Forum · ‎08-26-2013

You're right. The new code would be:

temp(i * 4) <= temp(...

Altera_Forum · ‎08-26-2013

I found another thread about this.

Sorry for my poor previous query.

What I was exactly looking for is a "programmable step" and not a step that has to stablish some logic between the index and my desired positions.

Something like

for i in begin to end loop (step n) generate...

Reading about this I seems that this feature isn´t availabe for concurrent generate as well as for sequential loops...

Is that correct?

Regards

Jaraqui

Altera_Forum · ‎08-26-2013

To learn about allowed VHDL constructs I suggest to read a text book or the LRM.

In the present case, these points should be considered:

- the range of sequential for loops as well as generate loops must be constant.

- you can achieve a variable range or a variable step size in sequential for loops by combining it with conditional statements

- this is impossible with generate statements by their nature