generating a pulse pattern in VHDL

[Altera_Forum]

Hi, 

I am trying to generate a pulse using DE2 developement board. I need to set the output high and create a delay and low again - again a different delay and high again. I did this using a counters, which is very ineficient and prone to delays.   Is there any other way of doing this and synthesis in DE2 board using Quartus2?   Thanks in advance!

[Altera_Forum]

counters or state machines can do that readily. Delay units will be in clk periods. You can also use the two clk edges then combine the results allowing you half clk period units. 

 If you want other delay units unrelated to clk then that technlogy is not available yet in fpgas. For example you can use Tco of registers or combinatorial delays but all are unpredictable.

[Altera_Forum]

I don't understand the meaning of ineficient in your post.

[Altera_Forum]

inefficient:- methods like using counters make errors due to gate delays. 

 In fact, what I am trying to do is to create the signals as in attached image.

[Altera_Forum]

--- Quote Start ---  inefficient:- methods like using counters make errors due to gate delays.   In fact, what I am trying to do is to create the signals as in attached image.  --- Quote End ---    But gate delays are innevitable when using a clock, down to a minimum period of 1 clock. If you're having problems with gate delays, increase the clock frequency.

[Altera_Forum]

What are you trying to achieve? A test signal generator? Multple phase shifted clocks can be a solution. But you have to care for correct synchronisation when crossing the clock domain boundaries.