generating netlists in quartus

Intel® Quartus® Prime Software

Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

generating netlists in quartus

1,217 Views

Hi,

I'm looking to find out how to generate netlists in quartus for use with LEC tools.

namely: synopsys Formality, Cadence Conformal, and Mentor Graphics formalpro.

I am having trouble finding documentation on the EDA netlist writer that suggests I can export netlists recognizable by all 3 tools mentioned above.

edit: is it even possible to output any other netlist file besides .vo files? There seems to be adequate support for COnformal LEC, but the other tools have been largely ignored.

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.