Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17249 Discussions

get synthesis report from quartus_map eventhough i have blackbox in my design

Altera_Forum
Honored Contributor II
1,139 Views

Hi all, 

 

I need to know the rough post-synthesis area occupation of my project. However, one module, which is instantiated in many places is still under development. I need to make this as blackbox(used synthesis translate_off and translate_on), but the outputs and inputs to and from this module should not be optimized in the modules this black box module is being instantiated. Currently almost all the logic is getting optimized. 

 

Help is much appreciated. 

 

regards, 

Sumanth
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
451 Views

using synthesis translate_on/off just removes the code from the design, hence why optimisations are occuring. You need to use the syn_black_box attribute applied to that entity. It will not tell you the resource usage for the black box, but it should keep the io without removing them

0 Kudos
Reply