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YSada
Beginner
1,037 Views

helloworld issue on cyclone V

Hello,

I'm trying to develop using Terasic C5P board, which has Cyclone V FPGA. And host pc is set up with Ubuntu 14.04 and Intel OpenCL 17.1.

My problem is that I cannot program `/root/intelFPGA/17.1/hld/board/c5p/tests/hello_world/bin/hello_world.aocx` via JTAG, although my JTAG usb is correctly connected to my board.

I got a following error message. And I also have tried to set up on CentOS because of this error, but the operation system force reboots during a configuration via JTAG.

root@sada:hello_world $ ./bin/host Querying platform for info: ========================== CL_PLATFORM_NAME = Intel(R) FPGA SDK for OpenCL(TM) CL_PLATFORM_VENDOR = Intel(R) Corporation CL_PLATFORM_VERSION = OpenCL 1.0 Intel(R) FPGA SDK for OpenCL(TM), Version 17.1   Querying device for info: ======================== CL_DEVICE_NAME = c5p : HPC Reference Platform CL_DEVICE_VENDOR = Terasic CL_DEVICE_VENDOR_ID = 4466 CL_DEVICE_VERSION = OpenCL 1.0 Intel(R) FPGA SDK for OpenCL(TM), Version 17.1 CL_DRIVER_VERSION = 17.1 CL_DEVICE_ADDRESS_BITS = 64 CL_DEVICE_AVAILABLE = true CL_DEVICE_ENDIAN_LITTLE = true CL_DEVICE_GLOBAL_MEM_CACHE_SIZE = 32768 CL_DEVICE_GLOBAL_MEM_CACHELINE_SIZE = 0 CL_DEVICE_GLOBAL_MEM_SIZE = 1073741824 CL_DEVICE_IMAGE_SUPPORT = true CL_DEVICE_LOCAL_MEM_SIZE = 16384 CL_DEVICE_MAX_CLOCK_FREQUENCY = 1000 CL_DEVICE_MAX_COMPUTE_UNITS = 1 CL_DEVICE_MAX_CONSTANT_ARGS = 8 CL_DEVICE_MAX_CONSTANT_BUFFER_SIZE = 268435456 CL_DEVICE_MAX_WORK_ITEM_DIMENSIONS = 3 CL_DEVICE_MEM_BASE_ADDR_ALIGN = 8192 CL_DEVICE_MIN_DATA_TYPE_ALIGN_SIZE = 1024 CL_DEVICE_PREFERRED_VECTOR_WIDTH_CHAR = 4 CL_DEVICE_PREFERRED_VECTOR_WIDTH_SHORT = 2 CL_DEVICE_PREFERRED_VECTOR_WIDTH_INT = 1 CL_DEVICE_PREFERRED_VECTOR_WIDTH_LONG = 1 CL_DEVICE_PREFERRED_VECTOR_WIDTH_FLOAT = 1 CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE = 0 Command queue out of order? = false Command queue profiling enabled? = true Using AOCX: hello_world.aocx Reprogramming device [0] with handle 1 MMD INFO : [acl0] failed to program the device through CvP. MMD INFO : executing "quartus_pgm -c 1 -m jtag -o "P;reprogram_temp.sof@1"" Info: ******************************************************************* Info: Running Quartus Prime Programmer Info: Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition Info: Copyright (C) 2017 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Fri Dec 21 18:57:18 2018 Info: Command: quartus_pgm -c 1 -m jtag -o P;reprogram_temp.sof@1 Info (213045): Using programming cable "C5P [1-2]" Info (213011): Using programming file reprogram_temp.sof with checksum 0x05EFD99C for device 5CGXFC9D6F27@1 Info (209060): Started Programmer operation at Fri Dec 21 18:57:23 2018 Info (209016): Configuring device index 1 Info (209017): Device 1 contains JTAG ID code 0x02B040DD Info (209007): Configuration succeeded -- 1 device(s) configured Info (209011): Successfully performed operation(s) Info (209061): Ended Programmer operation at Fri Dec 21 18:57:27 2018 Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings Info: Peak virtual memory: 478 megabytes Info: Processing ended: Fri Dec 21 18:57:27 2018 Info: Elapsed time: 00:00:09 Info: Total CPU time (on all processors): 00:00:02 MMD INFO : [acl0] PCIe-to-fabric read test failed, read 0xffffffff after 1 attempts mmd program_device: Board reprogram failed   Kernel initialization is complete. Launching the kernel...     MMD FATAL: acl_pcie.cpp:62: can't find handle -34 -- aborting host: acl_pcie.cpp:62: ACL_PCIE_DEVICE* get_pcie_device(int): Assertion `0' failed.

 

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3 Replies
HRZ
Valued Contributor II
60 Views

Does your board pass "aocl diagnose acl0"?

YSada
Beginner
60 Views

Yes it does.

 

I have doubts about my aocl flash. Is my JTAG USB cable is necessary after aocl flash? I have a experience to set up DE5a Net DDR4 and It wasn't needed.

root@sada:~ $ aocl diagnose acl0   Verified that the kernel mode driver is installed on the host machine.   Using platform: Intel(R) FPGA SDK for OpenCL(TM) Using Device with name: c5p : HPC Reference Platform Using Device from vendor: Terasic clGetDeviceInfo CL_DEVICE_GLOBAL_MEM_SIZE = 1073741824 clGetDeviceInfo CL_DEVICE_MAX_MEM_ALLOC_SIZE = 1072693248 Memory consumed for internal use = 1048576 Actual maximum buffer size = 1072693248 bytes Writing 1023 MB to global memory ... Allocated 1073741824 Bytes host buffer for large transfers Write speed: 816.17 MB/s [816.17 -> 816.17] Reading and verifying 1023 MB from global memory ... Read speed: 804.17 MB/s [804.17 -> 804.17] Successfully wrote and readback 1023 MB buffer   Transferring 8192 KBs in 16 512 KB blocks ... 553.19 MB/s Transferring 8192 KBs in 8 1024 KB blocks ... 646.89 MB/s Transferring 8192 KBs in 4 2048 KB blocks ... 752.08 MB/s Transferring 8192 KBs in 2 4096 KB blocks ... 791.50 MB/s Transferring 8192 KBs in 1 8192 KB blocks ... 792.19 MB/s   PCIe Gen2.0 peak speed: 500MB/s/lane   Writing 8192 KBs with block size (in bytes) below:   Block_Size Avg Max Min End-End (MB/s) 524288 548.95 553.09 536.97 537.99 1048576 638.44 646.89 634.02 631.68 2097152 745.32 752.08 743.03 742.59 4194304 788.59 791.50 785.71 787.58 8388608 792.19 792.19 792.19 792.19   Reading 8192 KBs with block size (in bytes) below:   Block_Size Avg Max Min End-End (MB/s) 524288 542.00 553.19 533.15 531.31 1048576 628.96 630.81 625.49 622.37 2097152 721.87 722.43 720.88 719.30 4194304 762.59 762.75 762.43 761.64 8388608 779.54 779.54 779.54 779.54   Write top speed = 792.19 MB/s Read top speed = 779.54 MB/s Throughput = 785.87 MB/s   DIAGNOSTIC_PASSED

 

HRZ
Valued Contributor II
60 Views

I have never used a PCI-E-attached Cyclone V board but for PCI-E-attached Stratix V and Arria 10 boards, after the initial programming via JTAG to enable the PCI-E core, the JTAG cable will not be required anymore (unless the PCI-E core breaks and JTAG reconfiguration is required again). Since diagnose is passing in your case, PCI-E transfer must be working correctly. However, for some reason, run-time FPGA reconfiguration seems to be going through JTAG instead of PCI-E. Unless Cyclone V does not support PCI-E-based reconfiguration, this should not happen.

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