i have problem with my vhdl code ,when i complie(in modelsim) there are no erros,but when test waveform the output alaways xxxxxxx,how to fix this
PS: my code base on "dsp with fpga" about adaptive filter,so i don't think it wrong????
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_arith.all;use ieee.std_logic_signed.all;entity ab is port ( xin :in std_logic_vector(7 downto 0); clk: in std_logic; y :out std_logic_vector(7 downto 0); y1 : out std_logic_vector(7 downto 0));end ab;architecture Behavioral of ab issubtype n1bit is std_logic_vector(7 downto 0);type array_n1bit is array(0 to 2) of n1bit;signal x : array_n1bit;signal f : array_n1bit :=((others=> (others=>'0')));begin process begin wait until clk='1'; x(0)<=xin; x(1)<=xin; f(0)<=f(0)+x(0); --f(1)<=f(1)+x(1); end process; y<=f(0); y1<=f(1);end Behavioral;
