help to setup timequest

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Dear Experts, 

i'm having difficulties to setup SDC file to behave. Could someone give me a hint?  Imagine, that you have a VME bus, where relation of data strobes (pVMEDSDxSNA) and data bus (pVMExDA) is given by VME bus timing: i.e. setup time of pVMExDA wrt pVMEDSDxSNA is 35ns, hold time is zero.  I'm synchronizing the data strobes using two flip-flops into 160MHz domain. Such synchronized signal I use as a clock enable to the register working at the same 160MHz to fetch the data appearing on the bus.  As it is guaranteed that the data disappear from the bus only and only at the moment when the third signal (DTACK) is asserted from my code, one can be sure, that the data stay and are correctly latched (as verified in hardware). The same applies for address strobe as well  In order to perform the design analysis I wrote a small SDC file:  1) CLOCK GENERATION ------------------------ create_clock -name "INTERNAL OSC" -period 25ns [get_ports {pClkDxC}] -waveform {0.000ns 12.500ns} create_clock -name "VME_ADDRESS_STROBE" -period 80ns [get_ports {pVMEAsDxSNA}] create_clock -name "VME_DATA_STROBE" -period 80ns [get_ports {pVMEDSDxSNA[0] pVMEDSDxSNA[1]}] create_generated_clock -name "CLK160MHZ" -source [get_pins {CLK160|altpll_component|pll|inclk[1]}] -duty_cycle 50.000 -multiply_by 4 -master_clock {INTERNAL OSC} [get_pins {CLK160|altpll_component|pll|clk[0]}]   2) REFER ADDRESS DATA AND STROBE TOGETHER set_input_delay -clock "VME_ADDRESS_STROBE" -max -28.75ns [get_ports {pVMEAddrDxDA[1] pVMEAddrDxDA[2] pVMEAddrDxDA[3] pVMEAddrDxDA[4] pVMEAddrDxDA[5] pVMEAddrDxDA[6] pVMEAddrDxDA[7] pVMEAddrDxDA[8] pVMEAddrDxDA[9] pVMEAddrDxDA[10] pVMEAddrDxDA[11] pVMEAddrDxDA[12] pVMEAddrDxDA[13] pVMEAddrDxDA[14] pVMEAddrDxDA[15] pVMEAddrDxDA[16] pVMEAddrDxDA[17] pVMEAddrDxDA[18] pVMEAddrDxDA[19] pVMEAddrDxDA[20] pVMEAddrDxDA[21] pVMEAddrDxDA[22] pVMEAddrDxDA[23] pVMEAddrDxDA[24] pVMEAddrDxDA[25] pVMEAddrDxDA[26] pVMEAddrDxDA[27] pVMEAddrDxDA[28] pVMEAddrDxDA[29] pVMEAddrDxDA[30] pVMEAddrDxDA[31] pVMELwordDxSNA}] -clock_fall  set_input_delay -clock "VME_ADDRESS_STROBE" -min 0ns [get_ports {pVMEAddrDxDA[1] pVMEAddrDxDA[2] pVMEAddrDxDA[3] pVMEAddrDxDA[4] pVMEAddrDxDA[5] pVMEAddrDxDA[6] pVMEAddrDxDA[7] pVMEAddrDxDA[8] pVMEAddrDxDA[9] pVMEAddrDxDA[10] pVMEAddrDxDA[11] pVMEAddrDxDA[12] pVMEAddrDxDA[13] pVMEAddrDxDA[14] pVMEAddrDxDA[15] pVMEAddrDxDA[16] pVMEAddrDxDA[17] pVMEAddrDxDA[18] pVMEAddrDxDA[19] pVMEAddrDxDA[20] pVMEAddrDxDA[21] pVMEAddrDxDA[22] pVMEAddrDxDA[23] pVMEAddrDxDA[24] pVMEAddrDxDA[25] pVMEAddrDxDA[26] pVMEAddrDxDA[27] pVMEAddrDxDA[28] pVMEAddrDxDA[29] pVMEAddrDxDA[30] pVMEAddrDxDA[31] pVMELwordDxSNA}] -clock_fall  The timings specified I calculated from the drawing shown in timequest wizard, i.e. max = 6.26ns-35ns, min=0   This appears to be working, however i'm not sure at all, whether it is specified correctly, especially taking into account that the maximum is specified _negative_ value.    What is the correct way to specify the timing for such case?   thanks a lot   david     ------------------- RELEVANT VHDL CODE -----------------------  --! @brief sync address strobe by 2ffs   many_ff_1 : many_ff  generic map (LATENCY => 2) --! [natural] total latency of the circuit  port map (ClkxC => Clk160MHzxC, --! [in std_logic] clock signal  ResetxRNA => ResetxRN, --! [in std_logic] reset signal  DxD => pVMEAsDxSNA, --! [in std_logic] input data  QxD => VMEAsxSN); --! [out std_logic] output data   --! @brief negative edge detection on address strobe helps to fetch address  ASCATCH : edge_detector  port map (ClkxC => Clk160MHzxC, --! [in std_logic] clock  pResetxRNA => ResetxRN, --! [in std_logic] standard reset  DxD => VMEAsxSN, --! [in std_logic] input data to be edge detected  QxD => open, --! [out std_logic] single clock pulse when positive edge detected  QxDN => VMEAsNxGS); --! [out std_logic] single clock pulse when negative edge detected   --! @brief catches address distributed on the VME bus  --! @details  --! <b>type : </b>sequential  --! <b>inputs :</b> Clk160MHzxC, ResetxRN  --! <b>outputs:</b>  --!  ADDRCATCH : process (Clk160MHzxC, ResetxRN) is  begin -- process ADDRCATCH  if ResetxRN = '0' then --! asynchronous reset (active low)  VMELwordxSN <= '1';  VMEAddrxD <= (others => '0');  VMEAMxD <= (others => '0');  elsif rising_edge(Clk160MHzxC) then --! rising clock edge  if VMEAsNxGS = '1' then  -- address strobe goes low, latch bus:  VMELwordxSN <= pVMELwordDxSNA;  VMEAddrxD <= pVMEAddrDxDA;  VMEAMxD <= pVMEAMDxDA;  end if;  end if;  end process ADDRCATCH;