help with counter

[Altera_Forum]

im trying to learn to create counter that starts counting based on the input that from the expansion after i compile it it seems an error occur and i dont know how to solve it. help me guys.. this error occured (Error (10500): VHDL syntax error at ledwithcounter.vhd(29) near text "then"; expecting ":=", or "<=") ....here i attach my program.. help me guys.. 

  Library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_unsigned.all;   entity GPIOwithLED is    port( GPIO_0 : in std_logic_vector(1 downto 0);  ld_enb : in std_logic;--parallel load enable,active high  clk : in std_logic;-- system clock  cnt_enb : in std_logic;--count enable, active high  rst_n : in std_logic;-- reset,active high  q : out std_logic_vector(1 downto 0)); end GPIOwithLED ;   architecture bufferwithGpio_arc of GPIOwithLED is begin  process(GPIO_0)  begin   if (GPIO_0(0)='1') then q<=GPIO_0(1 downto 0);  else q<= "00";  end if;  end process;      counter:process(clk,rst_n) is  begin   if ( rst_n='0' ) then   count <=(others=>'0');   else(clk'event and Clk ='1')then  if (ld_enb='1')then  count<=GPIO_0;  elsif(cnt_enb ='1')then  count <=count+1;  end if;   end if;  end process counter;   -- assigment ouput  q <= count;     end bufferwithGpio_arc;

[Altera_Forum]

--- Quote Start ---    counter:process(clk,rst_n) is    --- Quote End ---    remove the is    --- Quote Start ---    begin   if ( rst_n='0' ) then   count <=(others=>'0');   else(clk'event and Clk ='1')then    --- Quote End ---    use elsif  Finally you cannot assign to q twice(multiple drivers)

[Altera_Forum]

library ieee; 

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;  entity ledwithcounter is   port( GPIO_0 : in std_logic_vector(1 downto 0);  ld_enb : in std_logic;--parallel load enable,active high  clk : in std_logic;-- system clock  cnt_enb : in std_logic;--count enable, active high  rst_n : in std_logic;-- reset,active high  cnt_out : out std_logic_vector(1 downto 0);  q : out std_logic_vector(1 downto 0)); end ledwithcounter ;  architecture bufferwithGpio_arc of ledwithcounter is begin  process(GPIO_0)  begin   if (GPIO_0(0)='1') then q<=GPIO_0(1 downto 0);  else q<= "00";  end if;  end process;      counter:process(clk,rst_n)  begin     if ( rst_n='0' ) then   count <=(others=>'0');   elsif(clk'event and Clk ='1')then  if (ld_enb='1')then  count<=GPIO_0;  elsif(cnt_enb ='1')then  count <=count+1;  end if;   end if;   end process counter;   -- assigment ouput  cnt_out <= count;   end bufferwithGpio_arc;  i have already done what u have said and now a problem oocurs.. Error (10482): VHDL error at ledwithcounter.vhd(31): object "count" is used but not declared.. how does i elminted this error..

[Altera_Forum]

--- Quote Start ---  library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;  entity ledwithcounter is   port( GPIO_0 : in std_logic_vector(1 downto 0);  ld_enb : in std_logic;--parallel load enable,active high  clk : in std_logic;-- system clock  cnt_enb : in std_logic;--count enable, active high  rst_n : in std_logic;-- reset,active high  cnt_out : out std_logic_vector(1 downto 0);  q : out std_logic_vector(1 downto 0)); end ledwithcounter ;  architecture bufferwithGpio_arc of ledwithcounter is begin  process(GPIO_0)  begin   if (GPIO_0(0)='1') then q<=GPIO_0(1 downto 0);  else q<= "00";  end if;  end process;      counter:process(clk,rst_n)  begin     if ( rst_n='0' ) then   count <=(others=>'0');   elsif(clk'event and Clk ='1')then  if (ld_enb='1')then  count<=GPIO_0;  elsif(cnt_enb ='1')then  count <=count+1;  end if;   end if;   end process counter;   -- assigment ouput  cnt_out <= count;   end bufferwithGpio_arc;  i have already done what u have said and now a problem oocurs.. Error (10482): VHDL error at ledwithcounter.vhd(31): object "count" is used but not declared.. how does i elminted this error..  --- Quote End ---    You need to declare it after architecture keyword to be known e.g. signal count : std_logic_vector(1 downto 0) := "00"; -- just like ports but without in/out  or you better declare it as  signal count: unsigned(1 downto 0) := "00"; in this case you need to add final assignment to count_out as a cast : cnt_out <= std_logic_vector(count);  finally use numeric_std library instead of signed/unsigned libraries.

[Altera_Forum]

library ieee; 

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all;  entity ledwithcounter is   port( GPIO_0 : in std_logic_vector(1 downto 0);  ld_enb : in std_logic;--parallel load enable,active high  clk : in std_logic;-- system clock  cnt_enb : in std_logic;--count enable, active high  rst_n : in std_logic;-- reset,active high  cnt_out : out std_logic_vector(1 downto 0);  q : out std_logic_vector(1 downto 0)); end ledwithcounter ;  architecture bufferwithGpio_arc of ledwithcounter is begin  process(GPIO_0)  begin   if (GPIO_0(0)='1') then q<=GPIO_0(1 downto 0);  else q<= "00";  end if;  end process; end bufferwithGpio_arc;   architecture rtl of counterun is  begin  -- Local signal because it has to be read internally  -- unsigned type used because of "+" operation needed  signal count: unsigned(1 downto 0) := "00";  begin -- architecture rtl  counter:process(clk,rst_n)  begin   if ( rst_n='0' ) then   count <=(others=>'0');   elsif(clk'event and Clk ='1')then  if (ld_enb='1')then  count<=GPIO_0;  elsif(cnt_enb ='1')then  count <=count+1;  end if;   end if;   end process counter;   -- assigment ouput  cnt_out <= std_logic_vector(count); end architecture rtl;  i have follow all of your instruction.but stil there is error occur.Error (10500): VHDL syntax error at ledwithcounter.vhd(31) near text "signal"; expecting "end", or "(", or an identifier ("signal" is a reserved keyword), or a concurrent statement.... do i need to declare the port of my counter in separate ways from my input port. need clarifaication sir..

[Altera_Forum]

use one architecture 

also don't need library std_logic_arith

[Altera_Forum]

i have already done that now thiss error occur 

Error (10327): VHDL error at ledwithcounter.vhd(35): can't determine definition of operator ""+"" -- found 0 possible definitions

[Altera_Forum]

--- Quote Start ---  i have already done that now thiss error occur Error (10327): VHDL error at ledwithcounter.vhd(35): can't determine definition of operator ""+"" -- found 0 possible definitions  --- Quote End ---    where is your code?

[Altera_Forum]

ibrary ieee; 

use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all;  entity ledwithcounter is   port( GPIO_0 : in std_logic_vector(1 downto 0);  ld_enb : in std_logic;--parallel load enable,active high  clk : in std_logic;-- system clock  cnt_enb : in std_logic;--count enable, active high  rst_n : in std_logic;-- reset,active high  cnt_out : out std_logic_vector(1 downto 0);  q : out std_logic_vector(1 downto 0)); end ledwithcounter ;  architecture bufferwithGpio_arc of ledwithcounter is signal count : std_logic_vector(1 downto 0) := "00";  begin  process(GPIO_0)  begin   if (GPIO_0(0)='1') then q<=GPIO_0(1 downto 0);  else q<= "00";  end if;  end process;    counter:process(clk,rst_n)  begin   if ( rst_n='0' ) then   count <=(others=>'0');   elsif(clk'event and Clk ='1')then  if (ld_enb='1')then  count<=GPIO_0;  elsif(cnt_enb ='1')then  count <=count+1;  end if;   end if; end process; end bufferwithGpio_arc;   need to include the arith library then theres is no error. but it shows 9 warning..is that okey mr kaz

[Altera_Forum]

declare count as unsigned. 

 if the following is rejected then cast it: count <= unsigned(GPIO_0);

[Altera_Forum]

mr kaz  

 silly question from me.. the code works..but i would like to try this code using my alterra de2 board by using the pin assignment.. as for the input i simply connect it to my PIR sensors and the output will be my LED. so for the clock should use the 50Mhz internal clk and pushbutton for my rst_n.is that correct or not. ade how does i set for my cnt_enb and ld_enb.

[Altera_Forum]

I don't know what your plans are but sounds ok to me to use a 50MHz clock and manual pushbutton reset as long as it is suitable to your case!! Try and learn. All of us play with code until it works. If it doesn't you are in trouble.

[Altera_Forum]

tq mr kaz..  

sorry for troubling you.

[Altera_Forum]

Help with counter 

 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all;  entity AcounterGpio2 is  port( PIRin : in std_logic;  clk : in std_logic;  reset : in std_logic;  PIRout : out std_logic;  q : out std_logic);   end AcounterGpio2 ;  architecture bufferwithGpio_arc of AcounterGpio2 is signal cnt,enable: std_logic;  begin  process(PIRin)  begin  if PIRin = '1' then  PIRout <= PIRin ;  else PIRout <= '0';  end if;  end process;    counter:process (clk)  enable <= PIRout;  begin  if (rising_edge(clk)) then  if reset = '1' then  cnt := 0;-- Reset the counter to 0  elsif enable = '1' then  cnt := cnt + 1;-- Increment the counter if counting is enabled  end if;  end if;   -- Output the current count    end process counter;  q <= cnt; end bufferwithGpio_arc;  error Error (10500): VHDL syntax error at AcounterGpio2.vhd(29) near text "enable"; expecting "begin", or a declaration statement keep showing up.. what should i do and how do i declare the output from PIRout that will be the input for my counter.

[Altera_Forum]

First get rid of the ieee.std_logic_unsigned.all; and use unsigned and signed types, as suggested before. Second you can to signal assignments just after the process line. it needs to be after the "begin".