Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
14961 Discussions

hold timing and clock frequency considerations

Altera_Forum
Honored Contributor I
1,474 Views

hello all, 

 

two questions for the experts: 

 

1. why hold time is not frequency depended? 

 

2. will it be reasonable to assume that design that fits timing requirements with 100MHz clock frequency will also work properly with lower frequency clock? 

 

thanks.
0 Kudos
6 Replies
Altera_Forum
Honored Contributor I
86 Views

1. Hold time is pretty small compared to setup time. It is usually setup that is violated. 

2. Yes - if it met for 100Mhz, it will work for anything lower (IO may be different).
Altera_Forum
Honored Contributor I
86 Views

1. Hold time is based on the same clock edge, whereas setup time is based on consecutive clock edges. Thus hold time is not frequency dependent, whereas setup time will be. 

2. Tricky's answer is correct.
Altera_Forum
Honored Contributor I
86 Views

thanks to both of you. 

 

can you please elaborate about your answer to my second question? 

why it is ok to define the main clock of the design, lets say 100MHz, but actually inject to the fpga 80MHz clock?
Altera_Forum
Honored Contributor I
86 Views

Timing analysis checks to ensure the setup time is not violated. If you use a slower clock, the setup required period is the same, but the time between potential bit changes is now longer. So if it didnt break the setup timing before, it wont now.

Altera_Forum
Honored Contributor I
86 Views

for setup requirements i understand.  

but what about the hold requirements? skew? and other parameters? 

 

from my understanding, the skew is tailored according to specific clock that defined in the sdc file.  

it doesn't matter if we inject lower frequency that specified?
Altera_Forum
Honored Contributor I
86 Views

 

--- Quote Start ---  

for setup requirements i understand.  

but what about the hold requirements? skew? and other parameters? 

 

from my understanding, the skew is tailored according to specific clock that defined in the sdc file.  

it doesn't matter if we inject lower frequency that specified? 

--- Quote End ---  

 

 

hold is managed by fitter making sure that clock delay is never more than data delay (unless you gate the clock) 

skew and other delays are function of routing/temperature (not clock speed)
Reply