Hii'm using Quartus10.1 for startix iV gx evaluation board. during my synthesis i recieve the next info: info: design requires adding a large amount of routing delay for some signals to meet hold time requirements, and there is an excessive demand for the available routing resources. the fitter is reducing the routing delays of some signals to help the routing algorithm converge, but doing so may cause hold time failures. the synthesis ends with ~5 nsec hold violation can you assist thanks Meir
Hold issues are usually related to clock skew.A couple of possible causes: 1. Your design has an external clock that has been connected to a normal I/O pin instead of a dedicated input clock pin. 2. You have logic producing a clock (mux, divider, gate, etc).
thanksi do have some logic which generate clocks in the design i use single pll clock output and drive clock dividers the clock dividers outputs are the design clocks (divided by at leat 2 of the pll clock) i used clock groups to implify the falth_path between the clock groups is there any way to save this clock scheme and get the hold timing violation get convergence thanks
Try turning on "optimize all paths for hold timing".But the best course would be to replace the logic generated clocks with PLL generated clocks or clock enables.
Thanksthis is my default configuration i removed some of the logic i had on the clock tree and it seems to work even though i would like to check this logic in the fpga