how can i assign a node is not a clock

[Altera_Forum]

In the classic timing analyzer ，there is a instruction"not a clock" to assign a pin is not a clock,but i am using Timequest,how to i do?

[Altera_Forum]

From the Quartus II Handbook: 

 "The Not a Clock assignment directs the Quartus II Classic Timing Analyzer that the specified node is not a clock source when it would normally be detected as a clock because of a global fMAX requirement. The QSF variable for the Not a Clock assignment is NOT_A_CLOCK. This assignment is not supported in the Quartus II TimeQuest Timing Analyzer and there is no equivalent constraint. Appropriate clock constraints are created in the Quartus II TimeQuest Timing Analyzer only."  This assignment should not be required in TimeQuest. TimeQuest does a better job at recognizing which nets are clocks (and which are not) than the Classic Timing Analyzer does. If you think you have an application that requires this setting, please share it with us.

[Altera_Forum]

--- Quote Start ---  In the classic timing analyzer &#65292;there is a instruction"not a clock" to assign a pin is not a clock,but i am using Timequest,how to i do?  --- Quote End ---    You can use the Assignment Editor for setting this constraint.  Assignment -> Assignment Editor   to <pin name> assignment name Not a clock  Value on  Enabled yes

[Altera_Forum]

Timing Assignments made in the Assignment Editor are ignored by TimeQuest.

[Altera_Forum]

You can't, timequest is aware that the node is connected to a clock input of a flip-flop. So you have two choices: 

 1 - If the node is timing criticial, you can constrain it appropriately and tell timequest to analyze it as part of the data path. 2 - If the node is not timing critical, ignore it. Timequest will list it as an unconstrained clock but that's it, no harm done.  Jake

[Altera_Forum]

the signal "en_phase" is a external signal&#65292;i hope that the signal "sel_chop_brigde" change from 0 to 1,or 1 to 0 at the negedge of "en_phase", 

so i code this:  always @ (negedge en_phase)  sel_chop_brigde = ~sel_chop_brigde;  Timequest thinks the signal "en_phase" is a clock,how can i do to constraint this external signal&#65311; Thank you for your answers&#65281;&#65281;

[Altera_Forum]

How often do you expect the signal to transition from 1 to 0? 

 You could just pretend it is a clock and give a bogus low frequency.  Jake

[Altera_Forum]

--- Quote Start ---  How often do you expect the signal to transition from 1 to 0?  You could just pretend it is a clock and give a bogus low frequency.  Jake  --- Quote End ---   the fastest cycle is about 833us,and the lowest cycle is about 1s.