how to auto-assign the pins

[Altera_Forum]

I am using Quartus 2, I have a project that includes Cyclone 4. I have complicated deserialization and many LVDS pins. I want the tool to auto assign the pins. Even though the source code is ready with its top module and everything THE TOOL DOES NOT AUTO ASSIGN 

  Somehow the tool does not auto-assign the pins.   Can someone tell me clearly/step by step how to auto assign the pins of the FPGA using the Quartus.   best regards  Serkan

[Altera_Forum]

Err... what do you mean by auto-assign? 

The fitter will use an automatic assignmen to compile the design if you haven't yet done so. But to design the PCB, tou need to assign the pins manually.

[Altera_Forum]

I have nothing to do with the PCB. 

The fitter does not automatically assigns pins.   The tool does not assign pin locations to the signals on my top block/module.  For instance if I have input signal `clock` on my top block and I compile it  At the end of compilation when I open the pin planner I still see that the location and the I/0 bank of the signal is empty.

[Altera_Forum]

but why would you want it to assign signals to random pins? 

 on a real PCB, signals will HAVE to be mapped to specific pins. If you have no pcb, and you're only concerned about build size, why do you care what pin the signal is connected to?

[Altera_Forum]

Hi Drogio, 

Maybe this is a stupid question... Did you connect your top level to I/O signals? If you simply instantiated the block but you don't connect its ports to outer world, no pin will be assigned.

[Altera_Forum]

Of course of course. 

 Maybe the tool cant do this because of the warning I got from the tool.  Do you think the tool can not assign pins because it gives critical warning and cant find any pll for the required bank.  =============================================== Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Critical Warning: No exact pin location assignment(s) for 153 pins of 153 total pins  ...............................  Info: Pin iTile4SerClk not assigned to an exact location on the device  ................................... Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in target device due to device constraints

[Altera_Forum]

If you dont assign pins it will pick random pins for your signals. 

I suggest you constrain all your pins. The FPGA is pretty useless without doing so.

[Altera_Forum]

The thing is I could not make the tool pick random pins. 

 Why I want to do that? Because there are 6 different data channels to be serialized and 2 more clock inputs. I just need the basic information of tool assignments for clock inputs.  Let me Re-fine my Question What can be done wrong so that the tool does not pick random pins(the design is synthesizing and working tested)

[Altera_Forum]

To Tricky  

 Sorry for the misunderstanding. I am doing this of course for the PCB. I am doing this because I am familiar with Xilinx and Spartan FPGAs. I am not familiar to   Altera FPGA clocking structure  Altera IO structure Since I have many peripherals I just wanted the know if the selected FPGA is ok to do the deserialization and serialization or in which bank   I just wanted to see the automatically assigned clock inputs and outputs by PRESSING A BUTTON IN THE TOOL (like Xilinx) so that I will get some inspiration for my clocks (banks and pins)

[Altera_Forum]

PLLs on altera FPGAs usually have dedicated input pins. From the pin assignment, it works out which PLL to place into, rather than the other way round. 

 Regardless, the clock pins will already be connected on the PCB, so you have to assign it mannually anyway (regardless of whether its Xilinx or Altera).

[Altera_Forum]

`Regardless, the clock pins will already be connected on the PCB, so you have to assign it manually anyway (regardless of whether its Xilinx or Altera).` 

 I did not understand this above sentence and I think you are experiencing problems understanding my problem. Maybe you have not done any design that challenged you with the pins. First you need to understand that putting a input clock to dedicated clock pin is not the end. Even though you do that the design may not work. See below for the error   =========================================== Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in target device due to device constraints   Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_1 because location is already occupied by node "deserializer:tile1_deserializer|altlvds_rx:ALTLVDS_RX_component|deserializer_lvds_rx:auto_generated|lvds_rx_pll"  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_2 because location is already occupied by node "deserializer:tile6_deserializer|altlvds_rx:ALTLVDS_RX_component|deserializer_lvds_rx:auto_generated|lvds_rx_pll"  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_3 because location is already occupied by node "deserializer:tile5_deserializer|altlvds_rx:ALTLVDS_RX_component|deserializer_lvds_rx:auto_generated|lvds_rx_pll"  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_4 because location is already occupied by node "deserializer:tile4_deserializer|altlvds_rx:ALTLVDS_RX_component|deserializer_lvds_rx:auto_generated|lvds_rx_pll"  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_5 because location is already occupied by node "deserializer:tile2_deserializer|altlvds_rx:ALTLVDS_RX_component|deserializer_lvds_rx:auto_generated|lvds_rx_pll"  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_6 due to device constraints  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_6, because the PLL I/O pin Pin_T10 with port type INCLK is already occupied by node "iTile1SerClk"  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_6, because the PLL I/O pin Pin_T9 with port type INCLK is already occupied by node "iTile2SerClk"  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_6, because the PLL I/O pin Pin_L10 with port type INCLK is already occupied by node "iTile3SerClk"  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_6, because the PLL I/O pin Pin_L9 with port type INCLK is already occupied by node "iTile6SerClk"  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_7 due to device constraints  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_7, because the PLL I/O pin Pin_T10 with port type INCLK is already occupied by node "iTile1SerClk"  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_7, because the PLL I/O pin Pin_T9 with port type INCLK is already occupied by node "iTile2SerClk"  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_7, because the PLL I/O pin Pin_L10 with port type INCLK is already occupied by node "iTile3SerClk"  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_7, because the PLL I/O pin Pin_L9 with port type INCLK is already occupied by node "iTile6SerClk"  Error: Can't place MPLL or GPLL PLL "mainpll:mainpll_inst|altpll:altpll_component|mainpll_altpll:auto_generated|pll1" in PLL location PLL_8 because location is already occupied by node "deserializer:tile3_deserializer|altlvds_rx:ALTLVDS_RX_component|deserializer_lvds_rx:auto_generated|lvds_rx_pll" ===========================================   TO SUM UP I will have 8 incoming clocks  I do not know by heart which one should go to bank 1 which one should go to bank2 If I do myself tool gives errors.  I will make the tool auto-assign pins. (see it is not manual) I want to use this information