how to create matrix in VHDL

[Altera_Forum]

Hi guys! I am trying to create a matrix or an array. 4 columns and 2 rows. Is my code correct? 

 type row_t is array(0 to 3) of std_logic_vector(7 downto 0); type matrix_t is array(0 to 1, 0 to 3) of std_logic_vector(7 downto 0);  Also I want to assign a variable to the first column? what is the syntax for this? thank you.

[Altera_Forum]

Yes, it is a matrix 

2d matrices cannot be slices, so you need to assign individual elements. You could build it with 1d arrays, which can be sliced to apply an entire row.

[Altera_Forum]

what is the syntax for slicing a row?

[Altera_Forum]

like this (not possible with 2d array: 

 op <= matrix(a to b);  or  op <= matrix(b downto a);  You really need to try some code yourself - this is very basic VHDL fundamentals you should be learning yourself from a book or from a tutorial.

[Altera_Forum]

--- Quote Start ---  Yes, it is a matrix 2d matrices cannot be slices, so you need to assign individual elements. You could build it with 1d arrays, which can be sliced to apply an entire row.  --- Quote End ---    Excuse me for being pedantic but the OP asked how to assign a variable to the first column. Which is as tedious for a 1Dx1D as for a 2D array?