Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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17268 Discussions

how to fix this warning.

Altera_Forum
Honored Contributor II
‎12-08-2009 05:05 PM
1,445 Views

I got warning message from Quartus, don't know what its mean, the code works fine. just want to understand it. 

thanks 

 

Warning: At least one of the filters had some problems and could not be matched 

Warning: *ws_dgrp|dffpipe_se9:dffpipe18|dffe19a* could not be matched with a clock or keeper or register or port or pin or cell or partition
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Altera_Forum
Honored Contributor II
‎12-08-2009 05:36 PM
544 Views

The warning you are getting is from an invalid Timing Constraint. Most likely it comes from an "SDC" file created by some piece of Altera IP that you are using. It's probably not a problem. Many times, Altera's SDC scripts are so generic that they commonly make constraints on portions of the design that may not necessarily exist in your particular configuration. 

 

Jake
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Altera_Forum
Honored Contributor II
‎12-08-2009 08:38 PM
544 Views

correct. 

could it be that you use an ip where one output is not connected or an input is connected to vcc or gnd. in that case it could be that the synthese removes this pin but one of the sdc files has a contrain for it. due to the removement by the synthese this sdc constraine can not be matched.
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