how to implement a large memory on DE2 KIT ?

[Altera_Forum]

Hi everyone, I'm designing a LC3 CPU by quartusII on DE2 KIT. My problem is that I don't  

 know how to build a large memory, in my case is 2^16*16 bits. So I want to know how to   build it ?   I hope to get the answer soon !  Thanks you and best regarded !

[Altera_Forum]

hello long nguyen, u want 1Mbit?!!. it's not a good idea to build it using FPGA, even u can implement such large memory, the cost such money, power, etc is too expensive. A SDRAM may be an acceptable solution.

[Altera_Forum]

surely, I want to use SDRAM on DE2, but I dont know how to build it ? If you have any experience on it, pls mentor me :). 

 Thank you !

[Altera_Forum]

I have just test some sources, and recognized that if I intend use SDRAM on DE2 I have to use SOPC build in NIOS system. So it will be ridiculous because I dont intent work on high level system with C of ASM, rather I just desired use SDRAM for my CPU design. So Nios II system apparently useless! 

 In other hand, I suddenly think about how Nios system can use SRDRAM and I discovered that It has built-in SRDRAM controller. So as the result, if I want to exploit SRDRAM on DE2 I have to construct this one by my own or use some available IP SRDRAM controler.  Oh my god, now my question should be how to build a SRDRAM controller in quartus ?

[Altera_Forum]

--- Quote Start ---  recognized that if I intend use SDRAM on DE2 I have to use SOPC build in NIOS system  --- Quote End ---   No. You can use existing Altera code either VHDL or Verilog, to build a SDRAM controller. It's rather simple compared to a DDR RAM controller. See some previous forum discussions, e.g.: http://www.alteraforum.com/forum/showthread.php?t=2054

[Altera_Forum]

In several days, I have found some way to use SDRAM for my CPU, but it seems to be impossible.  

 Feeling disappoint, I decide to jot down something on this thread. :( !!!  - I try to use SDRAM controller of SOPC builder, but it needs avalon bus master.   look at all my process to design my CPU:  I have designed a Data Path and Control Path which further information below:  Datapath:  - ALU : 16 simple intructions - PSR PC, IR register - regiter file: 8 registers - mem (64K*16bits) - interupt module  Cotrol Path: - a list of state machine and decoded instructions  type of CPU is Von neumann/princeton ( it shares data and instruction memory) the method to deal with MEM is so complex, especially when I need to implement on DE2 Kit  It's clearly that I can't use M4K cell of Cyclon II because the synthesis is so long and waste resource. So the solution is SRAM or SDRAM integeratied in DE2 and this thing obey me need a SDRAM controller.   I have read some material relating SDRAM and I know that it's rather complex and need to well control with PLL. Moreover, in the level of hardware, I also need to take care AVALON bus.   It sounds good, isn't it ?  As I have mention above, I try to use SOPC to utilize available sdram controller. However, it can't work if not absence of NIOS II. SOPC builder seems to another aspect of design. So hopeless with it !!! I have to follow several procedure of SOPC builder and it not permit user control avalon bus, or I dont know how to do this work.

[Altera_Forum]

I feel so hopeless when no one can help me to my project. But finally, I has found the solution for it :) !!!

[Altera_Forum]

Maybe you could share some insight about how you have solved it, just in case someone else stucks in the same problem.

[Altera_Forum]

IF you want to use SDRAM or SRAM on DE2 Kit, you need to build your own an interface to there devices. However, it will be so complex but it's the the only way if you want to design a CPU with a large memory. In other word, you need to design a controller to interact between input and output data and this thing result in you have to truly understand the protocol read out and write in them.  

 Honestly, I haven't yet finished this controller so I can give them to every one in detail. However, If you want to reference, you can surf on the internet one page which possibly useful for this design. Here it's :  http://www1.cs.columbia.edu/~sedwards/apple2fpga/   The most important thing I found that If you intend design a CPU , dont be foolish to use NIOS-SOPC, you will depend on most it's architecture and that core and especially to avalon bus, it makes me confuse the FPGA architecture. Altera basically expect that we use their IP core as well as NIOS CPU so their tutor just trick our feel that it's snobbish but the fact that it is useless( at least in this design) and they transform us to their absolutely depended customer.