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how to implement a simple SERDES in VHDL?

Altera_Forum
Honored Contributor II
‎04-02-2015 08:53 AM
1,811 Views

Hi, 

I have a serial datastream and a DDR clock. I want to deserialize it to 12 bit parallel data and one clock, single edge. 

Is there anybody that can help me with it? Is there a design example? I use a Cyclone V. 

 

Thanks!
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Altera_Forum
Honored Contributor II
‎04-02-2015 04:26 PM
873 Views

Use the ALTLVDS_RX IP supplied (free) by Altera.

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