how to set those parameters of clock crossing bridge?

[ZhiqiangLiang]

Hi,

My FPGA model is Cyclone 10 LP 10CL120YF484.

on Platform Designer, NIOS frequency is 80MHz, and my IP is 160MHz.

In NIOS C code, I would like to read/write registers  of my IP.

In my design, I would like to add a Avalon-MM Clock Crossing Bridge between NIOS and my IP.

The questions are:

1) what do those parameters mean in Avalon-MM Clock Crossing Bridge setting?

2) in my design(NIOS 80MHz, IP 160MHz), how to set those parameters?

If no parameters can make my design work, what NIOS frequency should I set?

[KennyTan_Altera]

To connect your 80 MHz Nios to a 160 MHz IP, the Avalon-MM Clock Crossing Bridge should be the right solution and should work without changing your CPU frequency. The bridge safely manages data transfers between clock domains using FIFO buffers and synchronizers.

Key settings that you can try out:

• FIFO Depth: Start with 8–32 based on expected traffic.
• Synchronization Depth: 2 is standard and usually sufficient.
• Data Width: Match your system’s width (typically 32 bits for Nios and many IPs).
• Symbol Width: Usually set to 8 (1 byte per symbol).
• Burst Size: Set based on whether your IP supports burst transfers; otherwise use 1.
• Command/Response FIFO Depth: Larger values help if there's a lot of traffic or delay between domains.

In your case, the bridge should be configured with the Nios side as the master clock domain and the IP side as the slave. There's no need to increase Nios frequency—80 MHz is perfectly acceptable for this setup.

If performance issues arise, consider tuning FIFO depths or optimizing memory access patterns rather than increasing the processor clock.

Let me know if you have more question.

[ZhiqiangLiang]

@KennyTan_Altera 

Thank you! your explanation is very clear.

Your comments;

the bridge should be configured with the Nios side as the master clock domain and the IP side as the slave.

In my designed, I tried to connect master and slave of Clock Bridge reversed, but it can be run correctly. 

so I got confused. how should I connect master and slave.

solution 1: Clock Bridge master <---> NIOS and Clock Bridge slave <--> my IP.

solution 2: Clock Bridge master <---> my IP and Clock Bridge slave <--> NIOS.

[KennyTan_Altera]

When using an Avalon-MM Clock Crossing Bridge between an 80 MHz NIOS and a 160 MHz IP, connect the bridge’s master port to NIOS (the Avalon-MM master) and the slave port to the IP (the Avalon-MM slave). This ensures proper data flow and safe clock domain crossing. Reversing the connection may seem to work but can cause unreliable behavior. Always connect based on which side initiates the transactions.

[ZhiqiangLiang]

@KennyTan_Altera 

Thank you!

solution 1: Clock Bridge master <---> NIOS and Clock Bridge slave <--> my IP.

solution 2: Clock Bridge master <---> my IP and Clock Bridge slave <--> NIOS.

At present,  I really use solution 2 which is proved to be able to be run correctly in FPGA. 

That is why I asked the question again, and ask your conformation.

more information:

NIOS is 80MHz, and my IP is 160MHz.

NIOS will use the bus to write and read register in my IP. so, NIOS should be master and should be the one who initiates the transactions,right?

Are you sure I should choose solution 1 mentioned above?

[KennyTan_Altera · Accepted solution]

I reviewed some diagrams on the website, and based on what I saw, option 2 is actually the correct setup. The diagrams clearly indicate that option 2 is the proper way to connect.

https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/mm-clock-crossing-bridge-example.html

[ZhiqiangLiang]

@KennyTan_Altera 

Thank you!

according to the link you pasted above. your comments "connect the bridge’s master port to NIOS (the Avalon-MM master) and the slave port to the IP (the Avalon-MM slave)" is not correct, right?

[KennyTan_Altera]

That is correct, I think In Platform Designer, connections are typically restricted to slave-to-master and master-to-slave configurations, rather than allowing master-to-master connections.

[ZhiqiangLiang]

@KennyTan_Altera 

I got it. Thank you!

[KennyTan_Altera]

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