how to use case analysis to avoid multiple clock in TimeQuest

[Altera_Forum]

Currently in the design there is a mux to selec different clocks to trig a group of registers. For those clocks have the same frequency, but have different phase. In prime time , I can use case analysis to set the mux with a constant value to void multiple clock source problem. In TimeQuest, "multiple_clock Checks that registers have at most one clock at their clock pin. When multiple 

clocks reach a register’s clock pin, it is undefined which clock will be used for analysis." How can I do to avoid this in TimeQuest ?

[Altera_Forum]

I've heard of case analysis but don't fully understand it, so to be honest, I assume it does something impossible without. That being said, if two clocks go through a mux and there are two generated clocks on that mux output, and those two clocks are in different groups in the set_clock_groups assignment, then they won't be analyzed against each other, and when they connect to other clocks, you will get analysis under both conditions. So my assumption is that you would see both cases properly analyzed, and if you really want to remove one clock from analysis(say it's a test clock and won't properly connect to other logic), then it should be isolated with its own set_clock_groups assignment. That's how I would do it, but believe I am missing something in that analysis, so any further explanation as to what point I missed would be helpful.

[Altera_Forum]

I agree with what Rysc said, but I want to point out that you need to be careful if the clock mux is implemented in logic resources instead of a clock control block. See http://www.alteraforum.com/forum/showthread.php?t=2388.

[Altera_Forum]

Thanks! 

I try to use set_clock_groups to avoid this problem. For primetime case analysis, it's easy to understand, that is we set the select signal of mux to constant, the tool will ignore the mux , just select the according select signal to analysis.