Hello.. can anyone help me..
how to write verilog to display two 7-segment... i hav this verilog right now.. but when run, it will count double n double, randomly.. not follow the sequence 01, 02, 03,... until 59.. back to 00... i put 6 bit BCD input for this module, no error in this module but not follow what i want..
module sevenseg(s1, tens, ones);
input s1;
output reg tens;
output reg ones;
reg tensbcd;
reg onesbcd;
always@ (posedge s1)
begin
onesbcd <= s1 % 10;
tensbcd <= s1 / 10;
case (onesbcd)
0: ones = 7'b1000000; // 6,5,4,3,2,1,0
1: ones = 7'b1111001;
2: ones = 7'b0100100;
3: ones = 7'b0110000;
4: ones = 7'b0011001;
5: ones = 7'b0010010;
6: ones = 7'b0000010;
7: ones = 7'b1111000;
8: ones = 7'b0000000;
9: ones = 7'b0011000;
endcase
case (tensbcd)
0: tens = 7'b1000000;
1: tens = 7'b1111001;
2: tens = 7'b0100100;
3: tens = 7'b0110000;
4: tens = 7'b0011001;
5: tens = 7'b0010010;
6: tens = 7'b0000010;
7: tens = 7'b1111000;
8: tens = 7'b0000000;
9: tens = 7'b0011000;
endcase
end
endmodule
