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Valued Contributor III
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include file in a vhdl file ...

Hi,  

I need to include a computer generated vhdl file (including constants) in another vhdl file. I could generate the full file (so the header etc etc ) with my C code,  

but would be more clean to include the constants separately in the hand written file. Just to explain: 

CURRENTLY:  

use ieee.std_logic_unsigned.all; 

 

 

package common_defs is  

 

 

 

 

-- constant 

 

 

constant ENGINES_NUMBER : integer := 3; -- number of instanciated engines 

 

 

 

 

-- Types 

type INTERSECT is array (0 to 5) of std_logic_vector(11 downto 0); 

type INTERSECT_ARRAY is array (0 to ENGINES_NUMBER) of INTERSECT; 

 

 

 

 

 

 

constant ENGINE_INT_X : INTERSECT_ARRAY := ((X"010",X"020",X"030",X"040",X"050",X"060"), 

(X"010",X"020",X"030",X"040",X"050",X"060"), 

(X"010",X"020",X"030",X"040",X"050",X"060"), 

(X"010",X"020",X"030",X"040",X"050",X"060")) ; 

 

 

 

constant ENGINE_INT_Y : INTERSECT_ARRAY := ((X"011",X"021",X"030",X"040",X"050",X"061"), 

(X"011",X"021",X"030",X"040",X"050",X"061"), 

(X"011",X"021",X"030",X"040",X"050",X"061"), 

(X"011",X"021",X"030",X"040",X"050",X"061")) ;  

 

 

 

 

end common_defs; 

 

While I'd like something :  

 

use ieee.std_logic_unsigned.all; 

 

 

package common_defs is  

 

 

 

 

-- constant 

 

 

constant ENGINES_NUMBER : integer := 3; -- number of instanciated engines 

 

 

 

 

-- Types 

type INTERSECT is array (0 to 5) of std_logic_vector(11 downto 0); 

type INTERSECT_ARRAY is array (0 to ENGINES_NUMBER) of INTERSECT; 

 

 

 

 

INCLUDE constants.vhd; -- HOW DO I DO IT ????????????????????????????????????? 

 

 

 

 

end common_defs; 

 

 

 

and constants.vhd is like:  

 

constant ENGINE_INT_X : INTERSECT_ARRAY := ((X"010",X"020",X"030",X"040",X"050",X"060"), 

(X"010",X"020",X"030",X"040",X"050",X"060"), 

(X"010",X"020",X"030",X"040",X"050",X"060"), 

(X"010",X"020",X"030",X"040",X"050",X"060")) ; 

 

 

 

constant ENGINE_INT_Y : INTERSECT_ARRAY := ((X"011",X"021",X"030",X"040",X"050",X"061"), 

(X"011",X"021",X"030",X"040",X"050",X"061"), 

(X"011",X"021",X"030",X"040",X"050",X"061"), 

(X"011",X"021",X"030",X"040",X"050",X"061")) ;  

 

and it is computer generated.  

 

Is that possible ? 

thanks 

franco
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Highlighted
Valued Contributor III
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you define a package called constants and use it like you did the other libraries 

 

Use work.constants.all; 

 

There is no pre-processor in VHDL like there is in C or Verilog, so you cannot just include another load of text. It has to be a compiled package. 

 

PS, Why are you using the non-standard std_logic_unsigned library?
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