input clock pin to 4 PLLs in a way Quartus is happy with

[Altera_Forum]

I am not entirely sure how to get round this. I have one input clock pin (my main system clock) and would like to route it to all four corner PLLs in my Arria 2 device. The Arria device I am using only has the 4 corner PLLs. I am using the 4 PLLs to drive altmemphy DDR3 interfaces running at 400MHz. 

 Although it is physically possible to route the input clock to all 4 PLL inputs, the way the clock pin input paths are, you can only route a clock input pin to 2 PLLs in a way that Quartus is happy with. If you route to all 4 you get the following warnings on the PLLs the clock is not optimal for.   Critical Warning: PLL clock altmemphy_c_i|C_altmemphy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1] driven through clock routing. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated clock pin on the same side.   Critical Warning: PLL clock altmemphy_d_i|D_altmemphy_alt_mem_phy_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[1] driven through clock routing. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated clock pin on the same side.    Is there a way round this or do I have to do something on the outside of the chip such as sending my oscillator to two different inputs which meet the clock input pin to PLL requirement   Any guidance would be gratefully recieved.   C

[Altera_Forum]

i would route the clock to more dedicated clock inputs on the FPGA

[Altera_Forum]

The reduced jitter performance of internally routed clocks is well described in the device manual. In so far the warnings are correct. The more interesting question is, if it's still sufficient for your application. In my opinion, a 400 MHz DDR3 interface is challenging as such, you should avoid additional risks and connect the dedicated clock input. For standard applications, you can more easily ignore the warning.

[Altera_Forum]

I agree additional risk is not something I want to take on. 

 Do you mean you recommend driving the external oscillator into two different dedicated clock inputs to satisfy Quartus and avoid the internal jitter routing issues :confused:?   I have drawn the proposal in the picture attached.   Thanks for your answers. I do appreciate it :).