Hello, I know its a beginner question and I am reading the handbook also. However I would really appreciate if anyone can direct me to any example or give me some suggestion regarding the following. I am new in FPGA.I have a hardware module (initially done for asic) and I need to synthesize it on the FPGA board and use signaltap to debug. To do that, I need to assign the pin of my hdl design with the clock pin of the board. Isn't it correct? How can I do that ? I believe there is a top level file for every boards and I can just instantiate my module on that top level and port map the pins. Is there any other way? I already synthesized my design without any kind of pin assignment with toplevel.
Presumed it's compatible with the development board hardware, you can assign the pins of your design in pin planner or assignment editor.If you are connecting to many pins I/O pins or e.g. memory hardware of the board, it might be convenient to copy the pin assignment of an existing example design. You can either use identical pin names in your design and copy the pin assignment only, or copy the top level design with port definitions.