is "for loop" in counter looping according clock cycle?

[Altera_Forum]

Hi, all 

 I would like to create a adjustable delay counter using verilog. I use for loop inside. However, I notice that the for loop does not count base on clock cycle. Any mistake I done? Below is my coding:  always @(posedge clk or posedge rst_counter)  begin  if (rst_counter)   begin   abc <= 0;    end   else if (en_counter)   begin  for (i=0;i<= receiveSize; i++)  begin  if (i== receiveSize)  abc <= 1;   end       end  end

[Altera_Forum]

for loops unroll into parrallel hardware. So you have receivesize different comparitors all trying to set abc to 1. In your case, the lowest value of receiveSize will always win, and so is always set to that.

[Altera_Forum]

Keep in mind this isn't software. What you do with Verilog is construct hardware. A for statement from 0 to 9 generates 10 pieces of hardware that all run at the same time. Sometimes this is what you want, but in no way is it similar to what a for loop in software does.

[Altera_Forum]

Now i know that. Thanks so much for reply! :)

[Altera_Forum]

It didn't work for me either when I used a for loop in one of my first projects.