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14966 Discussions

issues in running CycV_SoC with DDR3 RAM on Dev_Kit

Altera_Forum
Honored Contributor I
1,319 Views

Hello, 

 

I am in an internship and my task is to perform a DDR3-SDRAM memory test on the "Cyclone V SoC Development Kit" with the Cycone V SX 5SCXFC6.. FPGA. 

( To see what the difficulties are and if there are any timing issues with the preconfiguration; later on, I will have to make some tests including a DMA controller for burst transfer)  

The RAM is a Micron MT41K256M16HA-125 1GB SDRAM. 

The tool chain is in Version 13.1. 

 

a) First of all I made a simple reference design (4 counting LEDs) in QSYS (Clk, NiosII, OnChip RAM, JTAG, Interval Timer, System ID Per. and PIO for the leds) to get in touch wih this Development Kit and it works fine. 

The clk is a extern 50Mhz oscillator, the reset is on the dip-switch and the PIO is connected to 4 FPGA-LEDs. 

 

b) Then I extended the proofed QSYS design by a PLL, which generates a 125Mhz reference clock for the "DDR3 SDRAM Controller with UniPHY" - IP block, and the DDR3 SDRAM Controller, in order to use the HMC "hard memory Controller" on the FPGA to access the connected DDR3 RAM. 

The DDR3 SDRAM Controller got a preconfiguration according to the Mircron SDRAM. 

I connected the signals of this RAM Controller according to the design example "Reference Design - Cyclone V Hard Memory Controller with Avalon-MM data width expanded for User ECC: Quartus II v13.1" 

The signals to the "memory" and the "oct" conduits for the controller are exported. 

The generation is successful. ( the report message says something about running a "<design-name>_hmc_ddr3_emif_p0_pin_assignment.tcl" after the "Analysis & Synthesis" step in Quartus. 

--> A question is, if it is possible to run this *.tcl file automatically (just for future or changed designs)? 

 

 

c) Then I changed the names of the signals in the top level entity according to the names of the "rm_cv_soc_dev_board.pdf" in the DDR3 SDRAM (FPGA) section. 

I also found an existing *.qsf-file in the "golden system reference design" (called bts_xcvr.qsf) which uses the FPGA-DDR3-SDRAM, but it does not contain any settings for the "OUTPUT_TERMINATION" for the fpga_sdram pins, just for the hps_sdram!? 

--> why does this golden reference design work or compile? 

Furthermore this reference qsf-file assigned the IO_STANDARD to "SSTL-15 CLASS I" for the ddr3_fpga signals, allthough the *_pin_assignment.tcl sets it to the IO_STANDARD "SSTL-135 CLASS I" 

 

After creating a new Quartus project, I started to modify the *.qsf-file to assign the signals of the top level entity to the correct pin positions. 

It is possible to run the "Analysis & Synthesis" step after the assignment and afterwards to run the "*_pin_assignments.tcl" file, which modifies the qsf-file again 

( it adds some settings for INPUT and OUTPUT_TERMINATIONs and the IO_STANDARDs for the signals of the HMC ) 

The IO_STANDARD is now " IO_STANDARD "SSTL-135" " and so different form the reference design. 

Furthermore I had some problems with the IO_STANDARD for the LED, Clk and Reset pins, because they were on the same IO-banks as the HMC and have 2,5V per default. So I changed them to SSTL-1.35V, just to see what happens next.  

Next step was to run the Fitter, which resulted in several errros and warnings. 

 

 

Report massage"... 

... 

Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time 

Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details 

Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. 

Info (174060): Created on-chip termination control block "termination_blk0"  

Info (174063): Created on-chip termination (OCT) RZQ pin "termination_blk0~_rzq_pad"  

Critical Warning (174073): No exact pin location assignment(s) for 1 RUP, RDN, or RZQ pins of 2 total RUP, RDN or RZQ pins 

Info (174074): RUP, RDN, or RZQ pin termination_blk0~_rzq_pad not assigned to an exact location on the device 

Error (175020): Illegal constraint of pin to the region (50, 0) to (83, 0): no valid locations in region 

Info (175028): The pin name: ddr3_fpga_dq[6] 

Info (175015): The I/O pad is constrained to the location PIN_AJ16 due to: User Location Constraints (PIN_AJ16) 

Error (175005): Could not find a location with: OCT_CAL_BLOCK_ID of 1 (1 location affected) 

Info (175029): AJ16 

Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter. 

Info (11798): Fitter preparation operations ending: elapsed time is 00:00:20 

Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. 

Info (169186): Following groups of pins have the same dynamic on-chip termination control 

Info (169185): Following pins have the same dynamic on-chip termination control: c5_NiosSys_DDR3_hmc_ddr3_emif:hmc_ddr3_emif|c5_NiosSys_DDR3_hmc_ddr3_emif_p0:p0|c5_NiosSys_DDR3_hmc_ddr3_emif_p0_acv_hard_memphy:umemphy|c5_NiosSys_DDR3_hmc_ddr3_emif_p0_acv_hard_io_pads:uio_pads|c5_NiosSys_DDR3_hmc_ddr3_emif_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst|delayed_oct 

Info (169066): Type bi-directional pin ddr3_fpga_dq[7] uses the SSTL-135 I/O standard 

... 

..." 

 

--> now i don't know what to do next, because rzq pin seems not to be connected correctly, eventhough i assigned the ddr3_fpga_rzq to a pin. 

 

--> maybe someone knows a reference design for my development kit, which uses the ddr3-sdram with the niosii or at least with the fpga, because this topic  

seems to get more complex as expected and i need this design to continue the next task.  

 

--> maybe someone can give me an advice if my workflow is incorrect or say what is cumbersome on my approach. maybe there is a simpler way to configure the qsf-file. 

 

If required, I can post the qsys design the other quartus files. Please feel free to ask me, if any questions are arising. 

 

I hope we can solve the simple problem together :) 

 

Kind regards,  

Roland
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3 Replies
Altera_Forum
Honored Contributor I
218 Views

Seems like I have the same issue. No solutions yet?

Altera_Forum
Honored Contributor I
218 Views

Hi Socrates, 

 

I fixed the issue with help from the customer support :) 

Currently I am running some memory tests and will post my solution soon. 

First of all the preconfiguration of the Micron RAM is the problem for the pin_assignment warnings, cause the supply voltage is "1.5V DDR3" and some memory initialization options have to be changed. Furthermore one should copy the "Memory Timing" + "Board Settings" from a reference design of the corresponding Evaluation Kit.  

Next problem is with the reset sequence and a possible deadlock when you auto generate a reset network.  

... there are some more points to be considered to fix the cirtical warnings concerning ddr timings, but I will show my results soon.  

 

Which board are you using? 

 

I hope this could help you a bit.  

Kind regards.
Altera_Forum
Honored Contributor I
218 Views

Any solution? Same problem as OP here.

Reply