jk flip flop usin dataflow model

[Altera_Forum]

How to design jk flip flop using dataflow model. 

When i run the code it shows an error "iteration limit reached". my vhdl code is    library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------- entity jkff_dataflow is port(j,k,clk,rst:in std_logic;  q,qbar:inout std_logic); end jkff_dataflow; -------------------------------------------------------------   architecture jkff_dataflow of jkff_dataflow is begin   q<=(((k and clk) and qbar) nor qbar) nor rst; qbar<=((j and clk) and q) nor q; end jkff_dataflow;

[Altera_Forum]

You hehe created a logic loop. Q depends on qbar, and q bar depends on q, so it gets in an infinite loop. Q and q bat styles not be linked. 

 Also, you should be using the clk signal as a clock, bout a logic signal.

[Altera_Forum]

--- Quote Start ---  You hehe created a logic loop. Q depends on qbar, and q bar depends on q, so it gets in an infinite loop. Q and q bat styles not be linked.  Also, you should be using the clk signal as a clock, bout a logic signal.  --- Quote End ---      so to design jk flip flop I need to use behaviour modeling. so I cannot write code by using data flow model.

[Altera_Forum]

In don't know what this data flow model is you're talking about. Vhdl describes a logic circuit, hence it can only be a behaviour. Your code just describes a logic loop.

[Altera_Forum]

--- Quote Start ---  so to design jk flip flop I need to use behaviour modeling. so I cannot write code by using data flow model.  --- Quote End ---    A data flow model is a higher-level construct. A JK flip-flop is just an implementation detail.