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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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keeping bdf and verilog synchronized

Altera_Forum
Honored Contributor II
‎08-12-2013 07:15 AM
1,044 Views

Hello all 

 

One nice feature of quartus II 13.1 is the creation of bdf (Schematics) files in a visual form. 

However, it may happen that you wish to convert you schematics to Verilog to add pieces that are easier defined using a text editor 

This can be done using File -> Create/Update -> Create HDL design from Current file 

 

Once you have changed the verilog, is there any way to synchronize the original bdf with the updated verilog ? 

As far as I can tell the File -> Create/Update menu has no option for this, am I missing something ? 

 

Thanks, Damiano
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Altera_Forum
Honored Contributor II
‎08-12-2013 08:03 AM
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Nope - you cannot create a BDF file from source code. You can only create a block to be added at a higher level. 

 

Even if you could, it would be a complete mess.
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