little code problem in simulation

Altera_Forum · ‎03-24-2014

Hello everyone,

I have a little code problem that I can't resolve.

All the signals are green except the "uit" signal.

Can anyone see in the code what the problem is ?

Thanks

Here is the file:

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

entity debouncer is

port (

clk: in std_logic;

clk_enable: in std_logic;

rst: in std_logic;

cha: in std_logic;

syncha: out std_logic

--up_down: in std_logic;

--count_out: out std_logic_vector(3 downto 0)

);

end debouncer;

architecture behav of debouncer is

signal pres_shift, next_shift: std_logic_vector(3 downto 0);

signal sh: std_logic;

begin

next_shift <= pres_shift;

--synchroon proces, geklokt

syn_count: process(clk,clk_enable)

begin

if rising_edge(clk) then

if rst = '1' then

pres_shift <= (others => '0');

else

pres_shift <= next_shift;

end if;

end process syn_count;

--combinatorisch proces, niet geklokt

com_shift: process(pres_shift, next_shift)

begin

if(next_shift = "0001") then -- dit is voor 4 bits

next_shift <= cha & pres_shift(3 downto 1);

else

next_shift <= (others => pres_shift(0));

end if;

end process com_shift;

end behav;

And here is the testbench:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_unsigned.all;

entity debouncer_tb is

end debouncer_tb;

architecture structural of debouncer_tb is

-- Component Declaration

component debouncer

port (

clk: in std_logic;

--up_down: in std_logic;

cha: in std_logic;

rst: in std_logic;

syncha: out std_logic;

--count_out: out std_logic_vector(3 downto 0)

clk_enable: in std_logic

);

end component;

for uut : debouncer use entity work.debouncer(behav);

constant period : time := 100 ns;

constant delay : time := 10 ns;

signal end_of_sim : boolean := false;

signal clk: std_logic;

signal rst: std_logic;

--signal up_down: std_logic;

--signal count_out: std_logic_vector(3 downto 0);

--signal cha: std_logic;

signal syncha: std_logic;

signal button: std_logic;

signal uit: std_logic;

signal clk_enable: std_logic;

BEGIN

uut: debouncer PORT MAP(

clk => clk,

rst => rst,

clk_enable => clk_enable,

cha => button,

syncha => uit);

--up_down => up_down,

--count_out => count_out);

clock : process

begin

clk <= '0';

wait for period/2;

loop

clk <= '0';

wait for period/2;

clk <= '1';

wait for period/2;

exit when end_of_sim;

end loop;

wait;

end process clock;

tb : PROCESS

procedure tbvector(constant stimvect : in std_logic_vector(1 downto 0))is

begin

--up_down <= stimvect(1);

button <= stimvect(1);

rst <= stimvect(0);

clk_enable <= '1';

wait for period;

end tbvector;

BEGIN

tbvector("00");

wait for 1*period;

tbvector("01");

wait for 3*period;

tbvector("00");

wait for 2*period;

tbvector("10");

wait for 3*period;

--tbvector("00");

--wait for 10*period;

--tbvector("10");

--wait for 10*period;

--tbvector("10");

--wait for 10*period;

--tbvector("00");

--wait for 10*period;

--tbvector("00");

--wait for 10*period;

--tbvector("01");

--wait for 10*period;

--tbvector("01");

end_of_sim <= true;

wait;

END PROCESS;

END;

Altera_Forum · ‎03-24-2014

Do you see that output signal syncha is driven anywhere? I don't.

Altera_Forum · ‎03-25-2014

Solution ?

I just downloaded a few courses. I will look again.

Thanks for the reply.