Timing issue

[Altera_Forum]

Hi ,  

i compile my project with Quartus and i have critical error :  "Timing requierements not met" and the TimeQuest Timing Analyzer painted red . The clk_in Frequency to the FPGA is 25MHz entered to internal PLL and spread to all the components : c0=25MHz,c1=100MHz . At the compilation report(painted red) : under Fast 1200mV 0c Model : Hold summery :   clk_in : slack = -0.129, End point TNS = -0.127 under worst case timing path : the signal lock at Rx comoponent that is sampled by clk_in has Clock skew =1.5, data delay=1.525,slack=-0.129 . i sampled the ports of my project using signal tap with the clk_in = 25MHz and the Transmitted signals working properley but the received signals not working properley .  how can i solve the timing issue ?  summery file attached .

[Altera_Forum]

Why do you have 1.5ns of clock skew? Is this from an incoming I/O port, or something within the device? (I/O always have clock skew, while internally you can often get around it). Basically, is this a real path that needs to be analyzed and meet timing, and does it make sense to have 1.5ns of skew?  

 If it's an I/O path, can you increase the delay chain in the I/O? Maybe assign the input register to a location further from the I/O? (It's really hard to say without more information, so just some quick ideas.)

[Altera_Forum]

Hi ,  

i didn't define anything at the sdc file except the cycle time of the input clk that entered to the PLL .  The signal lock is output port - his role is to Turn on Led when he low . i sample this signal with clk_in at the signal tap . i didn't define any thing about it at sdc file . is it matter if the clock skew is 1.5ns? do i need to change the sdc file ? or , do you suggest to add registers to the output path of lock in order to increase the delay ?  what about the Hold issue ?  thanks .