logging error in vhdl

[Altera_Forum]

I got this error several times: 

 my code gets successfully compiled but the error is   "Logging is not supported for this item"  why this error is displayed, can anyone tell !!!!!!

[Altera_Forum]

What is this item? is it memory, a variable, a signal, etc.? If you could give some more information on this message such as when it occurs and in which program it will make helping you a lot easier.

[Altera_Forum]

--- Quote Start ---  What is this item? is it memory, a variable, a signal, etc.? If you could give some more information on this message such as when it occurs and in which program it will make helping you a lot easier.  --- Quote End ---    error is:- Logging is not supported for this item: /camera/image  and in my test bench:-   GENERIC( fi_n: STRING :="hexi.dat" ; -- Input hex file name  tclk: TIME:= 100ns -- Clock speed  );  FILE image: TEXT OPEN read_mode IS fi_n;   what could be the possible cause ??

[Altera_Forum]

I am not completely sure, but I would say Modelsim knows how to open/handle the file, but it cannot show you the changes made. As to why, I do not know.

[Altera_Forum]

what is the meaning of "it cannot show you the changes made"..as i haven't made any changes

[Altera_Forum]

Files are not synthesisable - they are only for use in simulation

[Altera_Forum]

--- Quote Start ---  Files are not synthesisable - they are only for use in simulation  --- Quote End ---     any possible solution for this, to make the code run ??

[Altera_Forum]

Remove the file declaration and any use of it from your code.

[Altera_Forum]

if this file is only used in simulation, then you can put synthesis on/off pragmas around it: 

  <synthesisable code> --synthesis translate_off <stuff you dont want synthesised goes here> --synthesis translate_on <this area will be synthesised>

[Altera_Forum]

--- Quote Start ---  error is:- Logging is not supported for this item: /camera/image  what could be the possible cause ??  --- Quote End ---   Files cannot be logged. Presumably you receive this error in response to a command that you issued to 'log image'; This command could come from either typing it in at the command line or as part of a TCL script. But wherever it is that you have 'log image', you must remove the command. This will not affect the functionality of your testbench.  Kevin Jennings

[Altera_Forum]

--- Quote Start ---  Remove the file declaration and any use of it from your code.  --- Quote End ---   Why in the world would you do that? Removing the file presumably removes some input stimulus from the testbench. The problem is that files cannot be logged to a Modelsim log file, not that it is not valid VHDL.  Kevin

[Altera_Forum]

--- Quote Start ---  Why in the world would you do that? Removing the file presumably removes some input stimulus from the testbench. The problem is that files cannot be logged to a Modelsim log file, not that it is not valid VHDL.  Kevin  --- Quote End ---     As Tricky said this applies only for synthesis, for testbench it is ok, as long as you don't tell Modelsim to log the possible changes made.

[Altera_Forum]

any possible solutions please

[Altera_Forum]

--- Quote Start ---  any possible solutions please  --- Quote End ---  Post# 10 has the solution, read it and implement it. If you need more detail, you need to post more detail about what exactly you did that caused the error...as was described in post# 10 as well.  Kevin