Hi,
I am wondering how the differente amount of logic elements is realised in the two SoC Devices Cyclone V SX C5 and C6?
Relating to the "Cyclone V Device Overview", the C5 Device contains 85000 logic elements while the C6 contains 110000 logic elements. I have compiled my SoC design for both devices. The fitter reportfiles for the two compilations make it clear to me, that there are different amounts of ALMs etc on the two devices.
But on the other hand, relating to the "Cyclone V Device Datasheet", the size of the configuration .rbf is the same. That is true for my design too. Also when I open the chip planner for both devices, I get (what looks to me) the exact same device. That means same amount of rows with ALMs and M10k blocks etc.
So I don't understand where the difference in the amount of logic elements come from. Is it the same die with the same amount of logic elements and the Quartus II software is just limiting the use of the logic elements? Or is it another die and the Quartus II software is just showing a wrong floorplanning view?
