logiclock regions change locations after import (bottom-up compilation)

[Altera_Forum]

Hi All 

I am using bottom-up complilation. At the top-level, I have some partitions (logiclock regions) called inst0, inst1, ..., inst10. I have a lower-level design called "inst". I imported "inst" into inst0, inst1, ..., inst10 partitions in the top-level design.  The import was done successfully. However, the locations of logiclock regions inst0, inst1, ..., inst10 changed after import.  I had set the logiclock regions to have "Locked" states (but after 'import' the state changed to 'Floating'). What should I do to avoid the logiclock regions to change location after importing "inst" into inst0, inst1, ..., inst10 partitions(logiclock regions) . 　 I appreciate your help. 　 　

[Altera_Forum]

--- Quote Start ---  Hi All I am using bottom-up complilation. At the top-level, I have some partitions (logiclock regions) called inst0, inst1, ..., inst10. I have a lower-level design called "inst". I imported "inst" into inst0, inst1, ..., inst10 partitions in the top-level design.  The import was done successfully. However, the locations of logiclock regions inst0, inst1, ..., inst10 changed after import.  I had set the logiclock regions to have "Locked" states (but after 'import' the state changed to 'Floating'). What should I do to avoid the logiclock regions to change location after importing "inst" into inst0, inst1, ..., inst10 partitions(logiclock regions) . 　 I appreciate your help. 　 　  --- Quote End ---    Hi,  maybe it is a stupid question, but did you fix the logiclock region in the subproject also ? Did you import only the netlist ? Which Quartus version do you use ?  Did you get a Warning like this :  Warning: Import has detected multiple, locked, LogicLock regions in the current project with the same origin; the regions will be set to floating to avoid placement conflicts.  Info: Set LogicLock region "divider1:divider_inst2|divider1" to floating.  Info: Set LogicLock region "divider1:divider_inst3|divider1" to floating.  You got this Warning when you have locked the LogicLock Region in the subproject. Whe n you import the partition to different LogicRegions you have a conflict with the origin of the  regions. In order to avoid the problem Quartus changed the setting to floating for the origin.  Kind regards  GPK

[Altera_Forum]

Hi 

The lower level project has the assigned logiclock regions (as assigned in the top level project). So, there is no conflict between logiclock regions in the low and top level projects. I imported .qxf file. The version of the quartus is 9.1.  　 The only warning that I have which may be related to this issue is: Warning: Ignored routing constraints for partitions preserving relative placement to moved LogicLock regions Warning: Ignored routing constraints for partition "the name of the partition" Warning: Ignored routing constraints for partition "the name of the partition"  

[Altera_Forum]

I am suspicious that the problem is due to the fact that I am importing one sub-project into several partitions in the top-level design. However, I dont see why shouldn't I be allowed to do so.

[Altera_Forum]

--- Quote Start ---  I am suspicious that the problem is due to the fact that I am importing one sub-project into several partitions in the top-level design. However, I dont see why shouldn't I be allowed to do so.  --- Quote End ---    Hi,  that is excatly the problem. You have a qxp-file for one logiclock region with the preserved placement and routing. At least for the logiclock region which is identical  for the sub- and top project there should be no problem. For the other the tool must look to an identical placement and ,more difficult, routing. I would assume it is difficult to find locations for logiclock region which are 100% indentical in terms of routing resources.  Kind regards  GPK