loop error with more than 250 iterations

[Altera_Forum]

I am using the free web edition of Quartus II 11.0 sp 1. I have a nested for loop in a function eg: for (i=0; i<=2; i=i+1) followed by for(j=0; j<=2; j=j+1) and some code. This fails with the following message  

"Error (10119): Verilog HDL Loop Statement error at Sudoku2.v(843): loop with non-constant loop condition must terminate within 250 iterations".  However, if I change the parameters of the 2nd loop to for (j=3; j<=5; j=j+1) or for (j=6; j<=8; j=j+1) it compiles just fine. That is the only change I make, and in each case the loop executes a maximum of 9 times. I am puzzled and was wondering if anyone has any suggestions. I am happy to post the offending code if it would be helpful. Thanks in advance for any assistance. Regards, Geof

[Altera_Forum]

It sounds like you're going about HDL coding completly wrong. It is not like software, it is hardware. When you synthesise, loops are unrolled so that the worst case can be generated, hence the loop iteration limit. I dont know what your loop is doing, but it sounds like it's generating a long logic chain, which is not going to be very useful for you. 

 Did you draw out a sketch of the expected hardware before you wrote any code? HDL stands for Hardware description language, so if you dont know what you're describing, how do you expect to write the code?

[Altera_Forum]

--- Quote Start ---  in each case the loop executes a maximum of 9 times.  --- Quote End ---   This could be expected according to your post. But apparently the code contains something that causes more iterations. The discussion is pointless without knowing the actual code.

[Altera_Forum]

--- Quote Start ---  It sounds like you're going about HDL coding completly wrong. It is not like software, it is hardware. When you synthesise, loops are unrolled so that the worst case can be generated, hence the loop iteration limit. I dont know what your loop is doing, but it sounds like it's generating a long logic chain, which is not going to be very useful for you.  Did you draw out a sketch of the expected hardware before you wrote any code? HDL stands for Hardware description language, so if you dont know what you're describing, how do you expect to write the code?  --- Quote End ---    Thank you, Tricky, for your response. You are correct, of course, as I am trying to use my DE2-70 board as a microcontroller without setting one up using Qsys. In a nutshell, I am just playing with the board and was trying to write a Sudoku solver. I am doing a brute force attempt at trying numbers in each blank square using a FSM to control the placement of new numbers and the checking for duplicates. Everything works well except for the function that checks a quadrant for duplicates. That is where I get the error. What is puzzling to me is why changing the range in the 2nd "for loop" can suddenly cause the error to disappear. That makes no sense to me at all. As far as hardware goes, I am not a designer of hardware, I am a retired businessman who loves to play with microcontrollers and have found the FPGA world has some neat possibilities. So I was letting Quartus and Verilog do all of the dirty work so that I could watch everything progress (showing progress on the HEX display and the LCD). I have attached the function code in question if that is helpful. Again thank you for taking the time to respond and I would appreciate any further comments that anyone may have.

[Altera_Forum]

Your loop indices are constrained (0 ~ 2) at start but then inside the loops you increment i or j again. I haven't done any loop like that but I assume from your work that i or j will overflow relative to declared range.