minimum pulse width report in Quartus II with cyclone IV and ALTGX IP
Using Cyclone IV with ALTGX (also alt_c3gxb_reconfig) IP CORE, after QUARTUS II Compilation, Synthesis, etc. and TimeQuest.. I got a report of problem with minimum pulse width (timing of setup and hold have already fixed well). I tried to find any obligation to the clk or ref clk to this IP CORE. Still don't know where is the problem. I tried to connect 100MHz input and also 27MHz input. It looks like it doesn't fix the reported problem.. What should I check or change? Thanks. Lior.