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missing .sdc file...

Altera_Forum
Honored Contributor II
2,640 Views

hi all. 

 

i have this critical warning in my program during compilation.. the error says  

 

"Critical Warning (332012): Synopsys Design Constraints File file not found: 'xx.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 

 

how do i fix this? where can i find that file. what tool should i use? 

 

 

thanks 

 

BR, 

glenn
0 Kudos
9 Replies
Altera_Forum
Honored Contributor II
894 Views

You have to write it. 

See the TimeQuest cookbook and user guide. 

You should, at the very least, have a constrain for every signal used as clock.
Altera_Forum
Honored Contributor II
894 Views

i see..thanks. 2 questions though... i only have 2 signals used as clock. the global clock and an SPI-like clock from a microcontroller. how do i constrain them? is there a tutorial for writing .sdc? 

 

thanks  

 

BR 

glenn
Altera_Forum
Honored Contributor II
894 Views

ok. i looked for the tutorial and found the Basic SDC Example 

 

# Constrain clock port clk with a 10-ns requirement create_clock -period 10 # Automatically apply a generate clock on the output of phase-locked loops (PLLs)# This command can be safely left in the SDC even if no PLLs exist in the design derive_pll_clocks # Constrain the input I/O path set_input_delay -clock clk -max 3 set_input_delay -clock clk -min 2 # Constrain the output I/O path set_output_delay -clock clk 2 2 

 

 

question though, the 10ns period, what if i have, say, a 20Mhz clock, should the period be 50 ns.? what about the delay for the output, should i also put min and max value like in the input? i have an SPI-like clock for communication with a PIC microcontroller, do i have to use create_clock for that signal also? if use the SPI-like clock for inputs, should the delay in the input be based on that clock or the global clock? 

 

thanks 

 

BR 

glenn
Altera_Forum
Honored Contributor II
894 Views

Read this too: 

http://www.alterawiki.com/wiki/file:timequest_user_guide.pdf 

 

- Clock period is 1/frequency. So for a 20 MHz clock, it's 20 ns. 

 

- In general, both input and output delays are a range, so you should use -min and -max. But if your -min and -max values are the same, then you can just use one command like in that example. 

 

- Yes, you should also constrain the SPI clock. 

 

- Since the SPI signals are related to the SPI clock, you should constrain then to the SPI clock. 

 

 

However, I'm guessing, your main clock and your SPI clock are unrelated. Ie, you have no way to know their relative phases. 

This means that you need to use asynchronous clock domain crossing techniques whenever you move from one clock to the other. 

You should also add a "set_false_path -from [get_clocks clk] -to [get_clocks spi_clk]" so that TQ doesn't try to analyze those paths (which can't be analyzed).
Altera_Forum
Honored Contributor II
894 Views

Thank you very much. that really helps... 

 

you guessed it right. main clock and the SPI Clock are unrelated. But what do you mean by "asynchronous clock domain crossing techniques"? sorry, i'm a beginner. any reading materials for that?  

 

i'll add that set_false_path now... thank you very much 

 

BR 

glenn
Altera_Forum
Honored Contributor II
894 Views

Please correct me if I'm wrong.. 

 

-Constraining the clock to,say, 20 ns means that any change in state less than that period is not "considered" as a clock signal? 

 

-And, constraining the input/output delay means that the delay is always in the range set in the sdc file? the range set is based on base clock of the input/output?
Altera_Forum
Honored Contributor II
893 Views

I'm in a hurry so.. 

 

- http://www.fpga4fun.com/crossclockdomain.html 

 

 

- I'm not sure what your question is... Constraning a clock eans you're telling TQ that that signal is a clock, with a 20 ns period (rising edge at 0 ns, falling edge at 10 ns by default). 

 

TQ will then use that information and it's knowledge of the internals of the FPGA to make sure your design meets the timing requirements (ie, does not violate setup or hold times). 

 

- input/output delay constrains are used to tell TQ what's going on outside the FPGA. 

 

set_input_delay -min 2 -clock clk [get_ports my_input] 

set_input_delay -max 3 -clock clk [get_ports my_input] 

^^ This will tell TQ that the source of "my_input" will generate transitions on the rising edge of "clk" and the signal will be delayed 2..3 ns before reaching the FPGA's pin. 

 

set_output_delay -min 2 -clock clk [get_ports my_output] 

set_output_delay -max 3 -clock clk [get_ports my_output] 

^^ This will tell TQ that "my_output" will be be delayed 2..3 ns after leaving the FPGA's pin and that the receiver will capture it on the rising edge of "clk". 

 

Note: You use "clk" in the I/O constraints not because your FPGA uses it, but because that's what your source/destination chip is using for those signals.
Altera_Forum
Honored Contributor II
893 Views

hi.. thank you very much for a detailed explanation.. this really helps. i already updated my .sdc file and the critical warnings are gone.

AAjit2
New Contributor I
893 Views

Hi I'm modifying an existing project call vjuartcomm, and I have added the .sdc file called vjuartcomm however upon compilation I'm getting the error "Critical Warning (332012): Synopsys Design Constraints File file not found: 'vjatguart.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design."

The thing is I believe this to be an incorrect file, yet I'm unable to trace the source of this problem where I may correct this. I have gone through the settings and in everything I only see the .sdc file I created and all I know is that I get this error from the fitter. I tried running the fitter and timing analysis separately and I got no error, but upon full compilation this error came about. Any suggestions on how I can trace the source of origin for this error. Thanks!!

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