modifying pin assignments in Quartus II 10.1

[Altera_Forum]

Anyone know of the best way to change pin assignments in Quartus II 10.1? 

 Tried in Pin Planner to change pin assignment locations for some signals.   (1.) Tried just changing it to the desired location, which is already used  by another signal. Under location column, I selected the desired pin number, but the tool refuses to change it & gives the  following popup screen: Editing location assignment is not successful. The pin is already assigned. (2.) Next I tried to unassign the pin number of the node that already has the desired pin number by selecting the blank entry in the drop-down menu under the location column,  Value entered is not a valid location Got the same popup when I tried to unassign the pin number of the node whose pin number I originally wanted to change. (3.) I then disabled the location assignments for both node using the Enable column in pin planner & tried to unassign the pin numbers, but got the same popups as above. I don't want to just swap pins, since the signal whose pin number I'm moving the node to is being moved to some other pin number. Thanks, GMM

[Altera_Forum]

you can edit the project .qsf directly, or use the Assignment Editor

[Altera_Forum]

I find Assignment Editor much more suitable for pin assignments. It allows you to simultaneously assign several I/Os to one pin location, so you problem# 1 is no longer an issue. Pin Planner is more of visualization tool to me.

[Altera_Forum]

Or use Tcl scripts where you can define variables, loops, and as important, maintain nice comments on why you need the the assignment.

[Altera_Forum]

Hi, 

 Can anyone help me with this error in quartus?  I am using DDR2 memory with EP3C120F780C7 DDR2: U25 and U26 bottom chip  I think there is some problem with the pin assignment order to the memory pins.I have assigned the pins as mentioned in the manual.    Error: Cannot place pin mem_dq[0] to location AG22  Error: Can't place VREF pin AC18 (VREFGROUP_B4_N1) for pin mem_dq[0] of type bi directional with SSTL-18 Class I I/O standard at location AG22  Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 4 when the VREF pin AC18 (VREFGROUP_B4_N1) is used on device EP3C120F780C7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out.  How to change the continuous assignment?

[Altera_Forum]

Assignment editor worked like a champ, thanks GMM