Has anybody got this type of error message before:
Error: Following nodes require the same Clock Control Block CLKCTRL_R13
Error: Node "simple_design_sys:inst|altmemddr_1:the_altmemddr_1|altmemddr_1_controller_phy:altmemddr_1_controller_phy_inst|altmemddr_1_phy:altmemddr_1_phy_inst|altmemddr_1_phy_alt_mem_phy:altmemddr_1_phy_alt_mem_phy_inst|altmemddr_1_phy_alt_mem_phy_clk_reset:clk|altmemddr_1_phy_alt_mem_phy_pll:pll|altpll:altpll_component|_clk1" is currently placed at location counter C1 of PLL_12 with a Global Signal type of Auto
Error: Node "simple_design_sys:inst|altmemddr_0:the_altmemddr_0|altmemddr_0_controller_phy:altmemddr_0_controller_phy_inst|altmemddr_0_phy:altmemddr_0_phy_inst|altmemddr_0_phy_alt_mem_phy:altmemddr_0_phy_alt_mem_phy_inst|altmemddr_0_phy_alt_mem_phy_clk_reset:clk|altmemddr_0_phy_alt_mem_phy_pll:pll|altpll:altpll_component|_clk1" is currently placed at location counter C1 of PLL_6 with a Global Signal type of Auto
Info: Following PLLs have a fixed counter order and cannot be changed; they may have forced some signals to use the same Clock Control Block
I can't make sense out of it.
I have 2 DDR2 controller on the same bank of a Stratix 2 device. They each use a different PLL and Quartus fitter seems to be unable to allocate a correct routing for the clocks as it is using the same Clock control block for both of them. I don't know what I should do.
As I am just updating an existing design that was using legacy controllers, I have very limited flexibility
Thanks for your help!
