multiple constant drivers for net erro

[Altera_Forum]

Hi,  

I have this code reg signed final_additions ; // two multiply results added together and registered reg signed final_result; // sum of final_additions wire signed final_result_temp; wire signed coefficients ; genvar Counter_Result; generate for(Counter_Result = 0; Counter_Result < ((NUM_OF_TAPS/4)-1); Counter_Result=Counter_Result+1) begin : the_final_reult always @ (posedge clk or posedge reset) begin if (reset) begin final_result_temp<= 0; end else if (clear == 1) begin final_result_temp <= 0; end if (Counter_Result == 0) begin final_result_temp <= final_additions; end else begin final_result_temp <= final_result_temp+final_additions; end end end endgenerate always @ (posedge clk or posedge reset) begin if (reset) begin final_result <= 0; end else if (clear == 1) begin final_result <= 0; end else begin final_result <= final_result_temp; end end  When i launch the compilation i get this error: Error (10028): Can't resolve multiple constant drivers for net "final_result[33]" at custom_FIR.v(255). How can i correct this erros.  Thank you

[Altera_Forum]

--- Quote Start ---  Hi,  I have this code reg signed final_additions ; // two multiply results added together and registered reg signed final_result; // sum of final_additions wire signed final_result_temp; wire signed coefficients ; genvar Counter_Result; generate for(Counter_Result = 0; Counter_Result < ((NUM_OF_TAPS/4)-1); Counter_Result=Counter_Result+1) begin : the_final_reult always @ (posedge clk or posedge reset) begin if (reset) begin final_result_temp<= 0; end else if (clear == 1) begin final_result_temp <= 0; end if (Counter_Result == 0) begin final_result_temp <= final_additions; end else begin final_result_temp <= final_result_temp+final_additions; end end end endgenerate always @ (posedge clk or posedge reset) begin if (reset) begin final_result <= 0; end else if (clear == 1) begin final_result <= 0; end else begin final_result <= final_result_temp; end end  When i launch the compilation i get this error: Error (10028): Can't resolve multiple constant drivers for net "final_result[33]" at custom_FIR.v(255). How can i correct this erros.  Thank you  --- Quote End ---    Do you drive "final_result" anywhere else not shown in your code? I haven't done verilog for years but I believe you don't need generate as you are driving the same signals several times. since you want to add up all the additions in an accumulator in real time then I will run a hard counter and add according to its value. The generate statement is a compile time issue, isn't it?

[Altera_Forum]

Thank you for your helps. 

Yes i use the variable final_result on the rest of my code. I'm sorry i don't understand what do you mean exactly.  I need to calculate a sum of a table using always block, how can i do it without a generate block as you mentioned.  Thank you

[Altera_Forum]

--- Quote Start ---  Thank you for your helps. Yes i use the variable final_result on the rest of my code. I'm sorry i don't understand what do you mean exactly.  I need to calculate a sum of a table using always block.  Thank you  --- Quote End ---    let me put it this way. You are designing FIR filter based on an accumulator. This is done to save not just adders but multipliers. What you need to do in fact is not what you are up to. use one multiplier then mux into it h0,x0 then h1,x1 ...etc and let result add up in an accumulator until you clear it. you will mux inputs and clear final sum based say on a running counter that counts number of taps.

[Altera_Forum]

--- Quote Start ---  let me put it this way. You are designing FIR filter based on an accumulator. This is done to save not just adders but multipliers. What you need to do in fact is not what you are up to. use one multiplier then mux into it h0,x0 then h1,x1 ...etc and let result add up in an accumulator until you clear it. you will mux inputs and clear final sum based say on a running counter that counts number of taps.  --- Quote End ---    Yes a design a FIR design filter based on accumulator . For the multiplier and the adder are work very well and the result are saved on the table final_additions. The last block to do is to calculate the sum of this table which is the result of the filter. For the number of taps is defined as constant.

[Altera_Forum]

well you don't need those stages but if you are happy fair enough. The generate statement with (n) count tells the compiler to create designs (n) times. It is just a short way of writing code. The design will not create counter but just use it during compile time and the counter will then vanish from this world while any target signal repeated in the generate loop will complain of multiple drivers each pushing it one way or the other.  

so just run your counter and add up according to its value to index the temp result without generate. At least that is how vhdl works and assume verilog will not be that different.

[Altera_Forum]

I remove a generate statement but i get the same error.

[Altera_Forum]

Then you must show your code and where else you are driving(not reading) the final_result. 

 BTW you don'trealy need to make any table and waste memory or registers. all you need a mux => mult => add = register => feedback to adder and use counter to control the MAC.

[Altera_Forum]

Delaration of the variable 

reg signed taps ; reg signed initial_additions ; // addition between two taps, only used in symetric filters reg signed multiplications ; // initial_additions * coefficients reg signed final_additions ; // two multiply results added together and registered reg signed final_result; // sum of final_additions wire signed final_result_temp; wire signed coefficients ; wire signed Counter_Result=0;  This the modified section  always @ (posedge clk or posedge reset) begin if (reset) begin final_result <= 0; end else if (clear == 1) begin final_result <= 0; end else begin final_result_temp<=final_result_temp+final_additions; Counter_Result<=Counter_Result+1; if (Counter_Result==((NUM_OF_TAPS/4)-1)) begin final_result <= final_result_temp; final_result_temp <= 0; Counter_Result=0; end end end  Here i use final_result variable scfifo the_output_fifo ( .aclr (reset), .sclr (clear), .clock (clk), .data (final_result), .almost_full (fifo_half_full), .empty (fifo_empty), .q (source_data), .rdreq (read_fifo), .wrreq (tag) // tag delay pipeline matches when valid data pops out of "final_result" );

[Altera_Forum]

where do you count up. Is the multiple drive on counter now?

[Altera_Forum]

I think you edited and added counter later. Is the multiple drive on final_result or somewhere else?

[Altera_Forum]

Lets me show a code that's work may be can help you to locate the probleme: 

generate if(NUM_OF_TAPS == 4) assign final_result_temp = final_additions; else if (NUM_OF_TAPS == 8) assign final_result_temp = final_additions + final_additions; else if (NUM_OF_TAPS == 16) assign final_result_temp = final_additions + final_additions + final_additions + final_additions; endgenerate // after 16 taps this should addition should be done with registered stages always @ (posedge clk or posedge reset) begin if (reset) begin final_result <= 0; end else if (clear == 1) begin final_result <= 0; end else begin final_result <= final_result_temp; end end This code it work very well. The change that i need is to calculate the final_result_temp result using a genereic code. That's mean avoid the using of the if statement.  I hope that this code is more comprehensible.  Thanks

[Altera_Forum]

so basically you want to add in that order: 

taps = 4, add [0] only taps = 8, add [0] +[1] taps = 16, add [0]+[1]+[2]+[3]...etc  but your first generate statement is not doing that. I suggest you run a hardware counter as integer say from 0 to taps/4-1 and so it adjusts to number of taps. Then set your logic such that count is used as index.  that is something like this: sum <= sum+addition(count);   thus the feedback loop will take care of it as the counter runs.

[Altera_Forum]

see my edit. eventually your first loop counter is ok but you need to run counter in the design. so your final code was in the right direction i.e. the one you added counter in the logic.

[Altera_Forum]

Thank you very much Kaz, it work now, i will check the result tomorrow on the board. 

Thanks

[Altera_Forum]

When i add a counter, i get same error related to the count.

[Altera_Forum]

--- Quote Start ---  When i add a counter, i get same error related to the count.  --- Quote End ---    and where is the proof. show us your latest code showing error and what does error say.