not fit issue need your help

[Altera_Forum]

Error: Selected device has 26 RAM location(s) of type M4K. However, the current design needs more than 26 to successfully fit 

Info: List of RAM cells constrained to M4K locations Info: Node "     Above is the error i met.   I use EP2C5Q208C8 device. And i implemented 32 FIFOs in it, and met this kind of error. The FIFO is 256X1, that is the width is 1bit and depth is 256. So I think that just 2 M4K blocks are enough, but it seems it is not the fact.   Can anyone give me your advices? Thanks a lot!   Attached is my project, you can download and run it.

[Altera_Forum]

Memories can only be cobined if the address lines are running in parrallel. With fifos the whole point is that each fifo is run independently, so memory optimisation cannot occur (unless all of the write/read enables are driven from the same source). 

 Hence why its given each fifo it's own memory.  The fix would be to use no more than 26 fifos, or combine the words to more than 1 bit.

[Altera_Forum]

Looking at your design, you're not going to run into problems with just the fifos - You are putting a clock into a fifo - not a good idea. Use the clock to drive logic instead. 

 Also, all of your fifos are always written, but only read once every 32 clocks. That mean they are always going to be full, and the input is going to get lost.

[Altera_Forum]

as Tricky already said, memory blocks tith unsued bits are not combined. 

so you have 32 fifo's each 1 bit wide and 256 words deep. each fifo is build up with 1 M4K memory block, so from that you will need 32 M4K Memory blocks. each fifo is 1bit x 256 words = 256bit used out of 4096 bit (+512bit parity) each M4K has, the unused bits are wastesd and can not be re-used. you better rewrite these fifos to be 32bit x 256 words what means 16 bits will fit into 1 M4K memory block and the whole fifo should only use 2 M4K blocks so you will also need only 1 DelayCtrl.

[Altera_Forum]

Hi all: 

 Thanks for your reponse!   In my case, Ｉimplemented 32 individual fifos for these 32 signals are no relationship and being random each other, and these 32 signals must be delayed by different time. So i'm afraid that there would be some issue when combing with them.   I have checked the CII's datasheet, and found that the small memory can't be implement together into one m4k block.