open-drain/open collector type of output

[Altera_Forum]

Hi All, 

This might have been discussed before, but I didn't see a definite answer. I have one IO pins which I wanna assign it to be a open-drain type. I tried to add the following attribute to the VHDL:   ATTRIBUTE altera_io_opendrain : boolean;  ATTRIBUTE altera_io_opendrain OF timeout: signal is true;  Quartus II 9.0 Web gives me a "Warning (10335): Unrecognized synthesis attribute "altera_io_opendrain" at WATCHDOG/WDT.vhd(24)"  Anyone knows why? More, anyone knows a way to configure an IO pin as open drain type directly?  Thanks

[Altera_Forum]

Open drain is a regular tri-state output, that uses the states '0' and 'Z' only.

[Altera_Forum]

Try something like this.... 

output_pin <= '0' when (output_signal = '0') else 'Z';

[Altera_Forum]

Why not do that "pin assignments" in Quartus ?

[Altera_Forum]

altera_io_opendrain is a Synopsys synthesis attribute. It's not used by Quartus at all.

[Altera_Forum]

--- Quote Start ---  Open drain is a regular tri-state output, that uses the states '0' and 'Z' only.  --- Quote End ---    Actually, most FPGA and CPLD families have a dedicated Open Drain configuration control. See the IOE structure diagram.  I'm not sure what is the purpose of this Open Drain configuration, when it is not strictly needed. In most cases it won't even save user logic.

[Altera_Forum]

The open-drain configuration is required to allow the pin to sink current. 

Actually, Quartus will usually infer a IOE open-drain configuration from the code that gmstr posted.

[Altera_Forum]

--- Quote Start ---  The open-drain configuration is required to allow the pin to sink current.  --- Quote End ---    Sorry, I don't get why you would need a specific dedicated IOE configuration for that purpose.  If the data output at the IOE is permanently tied to ground, and the original data signal is negated and then used as Output Enable, then you effectively has an open drain output.

[Altera_Forum]

An open-drain output should be nothing more than a single mosfet with the source connected to the ground. And surely enough, a simple CMOS tri-state gate with D=0 will do just that. 

 But, and I'm speculating here, an FPGA IOE with it's many features (programable slew rate, programable current strenght, PCI clamp diode, etc, etc) might, somehow, behave a bit differently and Altera chose to add a bit of extra circuitry to make sure it behaves as expected from an open-drain.

[Altera_Forum]

Without knowing the exact transistor circuit of the output driver block, you can only guess about the purpose of a dedicated open drain feature. It could be better switching behaviour. And I imagine, it can be achieved by extending the current strength and impedance control by compeletely disabling the high side output transistors.

[Altera_Forum]

I guess that what you both are saying, is very possible. But then I would expect this to be mentioned somewhere in the literature.

[Altera_Forum]

Why don't working this bus-selector? 

 MAX3000A (EPM3032A or EPM3064A). Lines of both bus is pulluped by resistors 10K to VCC (+5).

[Altera_Forum]

After several tries, you finally succeded in showing an (almost) readable schematic. 

But what's not working?

[Altera_Forum]

--- Quote Start ---  After several tries, you finally succeded in showing an (almost) readable schematic. But what's not working?  --- Quote End ---    In the simulator all ok. Also I tryed add LCELL to adjust time-through of selection (see picture).  Real 74LS245 is working. But this schematic inside EPM3064A in same hardware don't working :-(.  What values of external pullups resistors is recomended?

[Altera_Forum]

--- Quote Start ---  But this schematic inside EPM3064A in same hardware don't working :-(.  --- Quote End ---   You're talking in riddles. I assume, that the schematic as such is working, but possibly the part isn't behaving as expected with the external circuitry.  Real 74LS245 hasn't open drain outputs, so it can't behave identically. Actually, I don't understand why you are using open drain at all? For the same reason, I can't recommend a pull-up value.

[Altera_Forum]

--- Quote Start ---  You're talking in riddles. I assume, that the schematic as such is working, but possibly the part isn't behaving as expected with the external circuitry.  Real 74LS245 hasn't open drain outputs, so it can't behave identically. Actually, I don't understand why you are using open drain at all? For the same reason, I can't recommend a pull-up value.  --- Quote End ---    I build the upgrade-like device (inside EPM3064A) for old hardware computer (Z80A). This device add some necessary fuction inside system. But. To avoid conflicts with the existing in the common to all bus, I try to select CPU's bus. In normal working it's simple bidirectional buffer (CPU<-BUS or BUS->CPU), when activated /BUSAK (CPU free the bus for the requested for it device) necessary to make true Z-state between bus of CPU & common for all BUS.  In some special cases EPM3064A must switch off common BUS, select CPU's bus only between internal port's device inside EPM3064A & CPU.  So. Really necessary in both sides of EPM3064A make true pulluped bus (beacose common Bus already pulluped (by 10K resistors). CPU's bus also have the opencollectors outputs & must to be pulluped.

[Altera_Forum]

--- Quote Start ---  You're talking in riddles. I assume, that the schematic as such is working, but possibly the part isn't behaving as expected with the external circuitry.  Real 74LS245 hasn't open drain outputs, so it can't behave identically. Actually, I don't understand why you are using open drain at all? For the same reason, I can't recommend a pull-up value.  --- Quote End ---    By the way, when I looking buses with the connected selector (EPM3064A) by oscilloscope, I'm visually see differents on both sides (data-bus in CPU side, & data-bus in common-bus side).  On the CPU<->EPM3064A side it's look (compared with side CPU-common bus) too tightened, when lelel goes from logic-zero to logic-one.  I hope it is because of too high resistance of pullups resistors. I try to reduse resistance of it.

[Altera_Forum]

The Z80 busses I'm aware of, e.g. ECB don't use open collector data lines. ECB has LS245 type tri-state drivers. In so far there's no problem of too high pull-up resistance values. Of course, open collector can work for rather slow (a few MHz) busses, but I would expect 470 ohm to 1k pull-up level. 

 The drawback with open collector drivers is, that a sufficient current strength is required for all bus members, so you surely can't operate an unbuffered CMOS or MOS peripheral, which can still work with a not to heavily loaded tri-state bus.