output Signal is not constant

[Altera_Forum]

Hello.. 

 I am making counter for quadrature ticks.Here i analyses my signal in Oscilloscope and here output signals are changing..as in it chaning from 1 to 0 n 0 to 1(Signal is not constant its changing even there is no input then also)  How can i stop it..As in is there any mistake in my code or how can i make my signal constant ??   library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.mem.all; Entity single is port(clk:in bit; msbinv:in std_logic; DOUT:in std_logic; OUT_PUT1:out std_logic_vector(12 downto 1); SCL:inout std_logic; NSL :inout std_logic); End Entity single; Architecture single_calc of single is signal counter : std_logic_vector(12 downto 1); begin trans:process(clk) variable cnt : integer range 0 to 160; begin if(clk'event and clk='1') then cnt:=cnt +1; if (cnt>=0 and cnt<3) then NSL <= '1'; elsif (cnt>=3 and cnt<6) then NSL <='0'; SCL <= '0'; elsif (cnt>=6 and cnt<9) then SCL <='1'; elsif (cnt>=9 and cnt<12) then SCL <= '0'; elsif (cnt>=12 and cnt<15) then SCL <='1'; elsif (cnt>=15 and cnt<18) then SCL <='0'; elsif (cnt>=18 and cnt<21) then SCL <='1'; elsif (cnt>=21 and cnt<24) then SCL <='0'; elsif (cnt>=24 and cnt<27) then SCL <='1'; elsif (cnt>=27 and cnt<30) then SCL <='0'; elsif (cnt>=30 and cnt<33) then SCL <='1'; elsif (cnt>=33 and cnt<36) then SCL <='0'; elsif (cnt>=36 and cnt<39) then SCL <='1'; elsif (cnt>=39 and cnt<42) then SCL <='0'; elsif (cnt>=42 and cnt<45) then SCL <='1'; elsif (cnt>=45 and cnt<48) then SCL <='0'; elsif (cnt>=48 and cnt<51) then SCL <='1'; elsif (cnt>=51 and cnt<54) then SCL <='0'; elsif(cnt>=54 and cnt<57) then SCL <='1'; elsif (cnt>=57 and cnt<60) then SCL <='0'; elsif (cnt>=60 and cnt<63) then SCL <='1'; elsif (cnt>=63 and cnt<66) then SCL <='0'; elsif (cnt>=66 and cnt<69) then SCL <='1'; elsif (cnt>=69 and cnt<72) then SCL <='0'; elsif (cnt>=72 and cnt<75) then SCL <='1'; elsif (cnt>=75 and cnt<78) then SCL <='0'; elsif (cnt>=78 and cnt<81) then SCL <='1'; elsif (cnt>=81 and cnt<84) then SCL <='0'; elsif (cnt>=84 and cnt<87) then SCL <='1'; elsif (cnt>=87 and cnt<90) then SCL <='0'; NSL <= '1'; cnt:= 0; end if; end if; end process trans; pros1:process(SCL,NSL) begin if(SCL'event and SCL ='1') then if NSL = '1' then counter <= "000000000000" ; end if; if NSL = '0' then if(msbinv = '1') then counter <= counter + "000000000001"; end if; if (msbinv = '0') then counter <= counter - "000000000001"; end if; end if ; end if; end process pros1; out_put1 <= counter ; End Architecture single_calc;    Please help me out..If my code is wrong then please give me some comment on it.  Thanking you.

[Altera_Forum]

You have SCL and NSL as inout ports, but it looks like you never use them as input pins. Do you intend process pros1 to get these signals from process trans and intend never to use these pins as inputs? If you are also driving these pins on the board but synthesis permanently enabled the tristate buffers, then that will cause problems. Check for synthesis messages like these: 

   --- Quote Start ---  Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus SCL~30 that it feeds Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus NSL~30 that it feeds Info: One or more bidirs are fed by always enabled tri-state buffers  Info: Fan-out of permanently enabled tri-state buffer feeding bidir "SCL" is moved to its source  Info: Fan-out of permanently enabled tri-state buffer feeding bidir "NSL" is moved to its source Warning: TRI or OPNDRN buffers permanently enabled  Warning: Node "SCL~644"  Warning: Node "NSL~588"  --- Quote End ---     With SCL in process pros1 being driven by a register in process trans, SCL is a ripple clock. Check your timing analyzer messages for that. You probably have clock hold violations for paths from the NSL register in the clk domain to the counter registers in the SCL ripple-clock domain being synchronously cleared by NSL. See my posts at http://www.alteraforum.com/forum/showthread.php?t=754 for more information about ripple clocks.   In more than place you use this coding style:  if my_signal = '1' then <do something> end if; if my_signal = '0' then <do something else> end if;   I would use this style instead:  if my_signal = '1' then <do something> else <do something else> end if;

[Altera_Forum]

I liked the detail in the ripple clocks posts. I read: Don't use them; stay in one clock domain. I used to think there were a handful of reasons to use ripple clocks, but now I only see one reason to use a Flip-Flop derived clock - because the frequency is lower than the minimum output of a PLL. (& tell Quartus to give it a clock buffer. ) One of the guys I work with goes farther and routes this flavor of clock out an output pin and back in a clock input pin. You can put a test pad on it, and it is super clear that it is a clock domain.  

 I did some coding just for an exercise, take a look if it is useful. [And if I attached correctly]

[Altera_Forum]

I think the problem may occur with the coding style. 

When you can use "case......when.......", it's better to use it instead of "if......else.....", because the if_else coding style is easy to cause output signal inconstant in some conditions like yours. Try it, it may work! Good luck!