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Altera_Forum
Honored Contributor I
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performance problems with std_logic_vector

I have a VHDL project that I build with Quartus. I developed the project with a signal std_logic_vector(0 to 15) and I have several places where I compare bits (0 to 3) with constant/literal values like "0000" or "1000". 

 

name: sig_out <= sig_out0 when select(0 to 3) = "0000" else sig_out1 when select(0 to 3) = "1000" else sig_out2 when select(0 to 3) = "0100" else sig_out3 when select(0 to 3) = "1100" else sig_out4 when select(0 to 3) = "0010" else sig_out5 when select(0 to 3) = "1010" else sig_default;  

 

When I change those statements to compare bits (12 to 15) the hardware runs significantly slower on the DE2-115 board. :confused: It's actually so bad that other parts of the hardware are failing. 

 

name: sig_out <= sig_out0 when select(12 to 15) = "0000" else sig_out1 when select(12 to 15) = "1000" else sig_out2 when select(12 to 15) = "0100" else sig_out3 when select(12 to 15) = "1100" else sig_out4 when select(12 to 15) = "0010" else sig_out5 when select(12 to 15) = "1010" else sig_default;  

 

Does anyone know why this is happening or have a solution?
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Altera_Forum
Honored Contributor I
42 Views

Im guessing those bits are generated from different logic. Without seeing how select is generated, its impossible to tell. 

Do you have any timing assignments? Have you run timequest? what do you mean by "it runs significantly slower? have you registered the outputs? is select registered? 

 

Post all the code so maybe we can get an idea.
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