Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15465 Discussions

post simulation does not support cyclone V?

jihunmoon
Beginner
273 Views

hi, i want to use post synthesis simulation (such as gate level simulation) in quartus.

I need sdo file from quartus to open in modelsim. But  I couldn't make sdo file and use this function with cyclone V in quartus. I read the quartus user guide and it said that post simulation doesn't support cyclone V. So I made sdo file and open it in modelsim with cycloen IV device.

I have a question. I think many people use cyclone V device, so is there a  no way to use post simulation with cyclone V device?? 

I 'm not saying about timing analysis in quartus. I'm saying about the post-sim using quartus and modelsim. 

0 Kudos
1 Solution
RichardTanSY_Intel
249 Views

Hi @jihunmoon 

 

Gate-level timing simulation is supported only for the Arria II GX/GZ, Cyclone IV, MAX II, MAX V, and Stratix IV device families.

Unfortunately, the gate-level timing simulation is not supported for Cyclone V device. 

 

We recommend that you use Timing Analyzer rather than gate-level timing simulation with any simulator. 

Reference:

https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-tp-simulation.pdf#...

 

You may checkout the User Guide below on how-to use the Timing Analyzer: 

https://www.intel.com/content/www/us/en/programmable/documentation/ony1529966370740.html

The tool is useful in analysis you design and to meet timing. 

 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

View solution in original post

3 Replies
RichardTanSY_Intel
250 Views

Hi @jihunmoon 

 

Gate-level timing simulation is supported only for the Arria II GX/GZ, Cyclone IV, MAX II, MAX V, and Stratix IV device families.

Unfortunately, the gate-level timing simulation is not supported for Cyclone V device. 

 

We recommend that you use Timing Analyzer rather than gate-level timing simulation with any simulator. 

Reference:

https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-tp-simulation.pdf#...

 

You may checkout the User Guide below on how-to use the Timing Analyzer: 

https://www.intel.com/content/www/us/en/programmable/documentation/ony1529966370740.html

The tool is useful in analysis you design and to meet timing. 

 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

jihunmoon
Beginner
236 Views
RichardTanSY_Intel
226 Views

You're welcome.  

I’m glad that your question has been addressed. With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

Reply