problem in compiling

[Altera_Forum]

Hi everyone, 

I am really new in using quartus to compile verilog design and new in verilog too. When i compile a simple verilog code using Quartus II, these error appear but I have no idea how to fix it. Could anyone please help me on it? I really appreciate your help.    Error: Top-level design entity "Part1" is undefined Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings  Error: Peak virtual memory: 191 megabytes  Error: Processing ended: Wed Mar 17 17:19:58 2010  Error: Elapsed time: 00:00:02  Error: Total CPU time (on all processors): 00:00:02 Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

[Altera_Forum]

You need to select your Verilog file as the top level for your design.

[Altera_Forum]

--- Quote Start ---  You need to select your Verilog file as the top level for your design.  --- Quote End ---     Hi,  additional check the module name of the toplevel. Be aware that Verilog is case sensitive.  Kind regards  GPK

[Altera_Forum]

Thanks guys, 

I got it. It works well now. :)