problem: multiply two fractional numbers in verilog

Altera_Forum · ‎12-24-2013

I have to multiply two fractional numbers of 42 bits in verilog. I am using the fixed point (Q12.30). Now my result is wrong.

part of my code:

module my_name (out,Clk)

input Clk;

output reg signed [83:0] out; //(Q24.60)

reg signed [41:0] in1; //(Q12.30)

reg signed [41:0] in2; //(Q12.30)

always @(posedge Clk)

out <= in1 * in2;

endmodule

for example if in1=-2 & in2=-1.89652 then out=3.79304 , but my result is -15956.351736 !!!

in modelsim:

-2 is 42'b111111111110_000000000000000000000000000000

-1.89652 is 42'b111111111110_00011010011111011010111100000

-15956.351736 is 111111111100000110101011_101001011111010010100010000000000000000000000000000000000000 (WRONG)

plz tell me how multiply two fractional numbers.

thanks.

Altera_Forum · ‎08-21-2014

It looks as though you have implemented an unsigned multiply rather than a signed multiply. It is treating -2 as 4094.0 and -1.89652 as 4094.10348

Altera_Forum · ‎08-23-2014

Besides wrong result sign, how can the compiler know that you are meaning fractional numbers? Obviously the result has to be scaled by a factor of 2^12, you should also apply saturation logic to avoid overflow to wrong result when cutting 12 bits on the left.