I have Quartus II V14 installed (64bits), also installed Modelsim Altera starter edition and set the path in the EDA tools section. This worked fine about a week ago and now I wrote some super simple code:
entity mux21 is
port ( a : in bit_vector(7 downto 0) ;
b : in bit_vector(7 downto 0) ;
s : in bit ;
y : out bit_vector(7 downto 0) ) ;
end entity mux21;
architecture arc_mux21 of mux21 is
signal s_bv : bit_vector(7 downto 0) ;
begin
s_bv <= (others => s) ;
y <= (a and not s_bv) or (b and s_bv) ;
end architecture arc_mux21 ;
After compiling, I created a VWF file and wanted to simulate. This is the msg I am getting:
http://s29.postimg.org/wnp0awutj/mdlsimerr.png And Modelsim tells me this means:
--- Quote Start ---
Message# 3063:
The specified VHDL port cannot be found by that name in the Verilog
module to which it is being connected. Verify that the correct
VHDL/Verilog connection is being made and that extended identifiers
are being used if necessary.
[DOC: ModelSim User's Manual - Mixed VHDL and Verilog Designs Chapter]
--- Quote End ---
I have no idea what is wrong here but I would be happy to get some help with this... Thanks!
