problem with HSMC

Altera_Forum · ‎12-03-2010

Hello.

I use Cyclone III starter kit and I program with vhdl .I don't use block symbol file.

I want to use pin of HSMC rx and tx(HSMC_TX_p4-HSMC_RX_p11) like general purpose data(HSMC_D0-D19).

I will wait for advice.

Thanks.

Altera_Forum · ‎12-06-2010

Just assign your signals to the correct FPGA pins in the pin planner.

Altera_Forum · ‎12-07-2010

I am very embarrasses to very few number of general I/O.

I am wonder why Altera HSMC specification has so much rx tx pin.

I do not think 12 set of LVDS connection is over spec.

My usage is general control, then I need more general I/O.

In this case, if I use three set of Cyclone III starter board, and One is host and other two are controller and communicate by LVDS,

I can seem to solve many control task using general I/O and USB communination with PC.

Is that right ?

Altera_Forum · ‎12-07-2010

rx and tx are just conventions, you can use them in any direction you want. But you need to keep the pairs together if you use them as LVDS (i.e. HSMC_TX_p4 and HSMC_TX_n4 together, but not HSMC_TX_p4 with HSMC_RX_p11).

For the pins that you use as general I/O if you don't use LVDS you can use any pin as you want, as input or output.

If you have a lot of data to move from/to the PC, it may be easier to use the Ethernet port. The embedded USB Blaster only allow communication through JTAG, and you would need to use a virtual JTAG component or the JTAG uart.

Altera_Forum · ‎12-07-2010

Thank you very much your advise.

I connected output pin using HSMC_TX_p4 and HSMC_TX_n4.

I use input data port for HSMC_D*. My program works.

But I connected output pin using HSMC_TX_p4 and HSMC_TX_n4.

And also I connected input pin assignment (LVTTL,3.3V standard) for

HSMC_RX_n4 and HSMC_RX_P4.

My program does not work.

We set port section as follows.

rx_in : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

rx_out : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

tx_in : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

tx_out : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

I am appreciate, if you suggest further configuration.

Altera_Forum · ‎12-08-2010

I don't see any problem with you port section, even if you could use STD_LOGIC instead than STD_LOGIC_VECTOR(0 DOWNTO 0) for a single bit, but this doesn't change anything to the design.

Try to put signaltap probes on your signals to find out what is going on.