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Valued Contributor III
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problems with real data type conversion to std_logic_vector

Hi, I'm doing an discrete PID controller, based on FPGA's, but I wanna do it using floating point maths, the first block I was doing was an integrator, but I got an issue, the generic parameters of my project are real values, and the port of the megawizard IP is an std_logic_vector (31 downto 0), i don't know how to cast from real to std_logic_vector(31 downto 0), here my code: 

 

Library IEEE; 

 

 

use IEEE.STD_LOGIC_1164.ALL; 

--use IEEE.STD_LOGIC_ARITH.ALL; 

--use IEEE.STD_LOGIC_UNSIGNED.ALL; 

use IEEE.math_real.all; 

use IEEE.numeric_std.all; 

 

 

 

 

entity bloque_integrador is 

generic 

sample_time : real :=1.0e-3; 

gain : real :=1.0 

); 

port  

clk_50MHz : in std_logic:='0'; 

clk_sys : in std_logic :='0'; 

rst : in std_logic:='0'; 

 

 

int_in : in std_logic_vector(31 downto 0):=X"00000000"; 

int_out : out std_logic_vector(31 downto 0) 

); 

end entity bloque_integrador; 

 

 

 

 

architecture structural of bloque_integrador is 

-------señales de conexion internas al modulo----- 

signal int_in_reg : std_logic_vector(31 downto 0);  

signal int_in_reg_amp : std_logic_vector(31 downto 0);  

signal int_out_reg : std_logic_vector(31 downto 0); 

signal acumulador : std_logic_vector(31 downto 0); 

signal clk_sys_n : std_logic; 

-------constantes del sistema----------------- 

 

 

constant factor_amplificacion : real:=(sample_time*gain); 

signal factor_amplificacion_vector : std_logic_vector(31 downto 0); 

-----------------componente multiplicador------------- 

COMPONENT amplifier_altfp_mult_nvo IS  

PORT  

(  

aclr : IN STD_LOGIC := '0'; 

clk_en : IN STD_LOGIC := '1'; 

clock : IN STD_LOGIC; 

dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 

datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 

result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) 

);  

END COMPONENT amplifier_altfp_mult_nvo; 

----------------componente sumador--------------- 

 

 

COMPONENT sumador_altfp_add_sub_t8k 

PORT ( 

aclr : IN STD_LOGIC ; 

clk_en : IN STD_LOGIC ; 

clock : IN STD_LOGIC ; 

datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 

dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 

result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) 

); 

END COMPONENT; 

 

 

begin  

-------------------declaraciones adicionales------------ 

factor_amplificacion_vector<=to_stdlogicvector(to_bitvector(factor_amplificacion)); 

clk_sys_n<=not(clk_sys); 

--------------declaracion del registro de entrada------------ 

reg_in: process(clk_sys, rst, int_in, int_in_reg) 

begin  

if rst='1' then int_in_reg<=(others=>'0'); 

elsif( clk_sys'event and clk_sys='1') then  

int_in_reg<=int_in; 

end if;  

end process reg_in; 

 

 

--------------declaracion del registro de salida------------ 

reg_out: process(clk_sys, rst,acumulador, int_out_reg) 

begin  

if rst='1' then int_out_reg<=(others=>'0'); 

elsif( clk_sys'event and clk_sys='1') then  

int_out_reg<=acumulador; 

end if;  

end process reg_out; 

 

 

----------------componente multiplicador---------------- 

multiplicador: amplifier_altfp_mult_nvo 

PORT MAP 

(  

aclr => rst, 

clk_en => clk_sys_n, 

clock => clk_50MHz, 

dataa => factor_amplificacion,  

datab => int_in_reg, 

result => int_in_reg_amp 

);  

 

---------------componente sumador---------- 

suma:sumador_altfp_add_sub_t8k 

PORT map ( 

aclr =>rst, 

clk_en => clk_sys_n, 

clock => clk_50MHz, 

datab => int_in_reg_amp, 

dataa => int_out_reg, 

result => acumulador 

);  

 

------------------------------ 

int_out <=int_out_reg; 

 

end architecture structural; 

 

 

thank you for read, I'll apreciate your help.
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4 Replies
Highlighted
Valued Contributor III
23 Views

the IEEE floating point package that became a standard with VHDL 2008 will have the conversion function you need. For a '93 compatible version you can compile into your project, see here: http://www.vhdl.org/fphdl/

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Highlighted
Valued Contributor III
23 Views

Also, when you use this, factor_amplificacion_vector should be declared constant, because it never changes.

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Highlighted
Valued Contributor III
23 Views

thank you, I'm downloading the libraries, you have been so kind.

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Highlighted
Valued Contributor III
23 Views

 

--- Quote Start ---  

the IEEE floating point package that became a standard with VHDL 2008 will have the conversion function you need. 

--- Quote End ---  

 

It looks like the OP intends unsigned integer arithmetic, the real to unsigned conversion can be done without additional libraries.
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