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Hi,
I am trying to write Verilog code to generate 1.a set of lower frequency clocks with certain step size from a 50mhz 2.then duty cycle varied each of these frequency In program 3 counters used. counter> to generate lower frequency clocks counter1> to vary duty cyle counter2>to select frequency value in compilation itself there is error in code.please help me .... ThankyouLink Copied
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Hi got solution from
http://quartushelp.altera.com/12.0/mergedprojects/msgs/msgs/evrfx_veri_procedural_assignment.htm Thankyou
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