Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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quartus prime software quit unexpectedly

Altera_Forum
Honored Contributor II
1,766 Views

I have problem with synthesis. I can't find any information about this error code.  

Here is the report: 

problem details 

Error: 

 

*** Fatal Error: Access Violation at 0X00007FFAFF18ED5E  

Module: quartus_map.exe  

Stack Trace:  

0x1ed5d: HDBX_READER::generate_dependencies + 0x39d (db_hdbx)  

0x1e3f0: HDBX_READER::generate_assignments + 0xbb0 (db_hdbx)  

0x1f507: HDBX_READER::generate_hdb + 0x107 (db_hdbx)  

0x22775: HDBX_READER::read_common + 0x155 (db_hdbx)  

0x5068: hdbx_drl_hdbx_read + 0x88 (db_hdbx)  

0x22dc4: QSYN_FRAMEWORK::write_qic_databases + 0x514 (quartus_map)  

0x21f24: QSYN_FRAMEWORK::write_databases + 0x114 (quartus_map)  

0x11378: qexe_do_normal + 0x2a8 (comp_qexe)  

0x16142: qexe_run + 0x432 (comp_qexe)  

0x16e51: qexe_standard_main + 0xc1 (comp_qexe)  

0x1b06b: qsyn_main + 0x51b (quartus_map)  

0x13328: msg_main_thread + 0x18 (CCL_MSG)  

0x14b0e: msg_thread_wrapper + 0x6e (CCL_MSG)  

0x15b00: mem_thread_wrapper + 0x70 (ccl_mem)  

0x12a11: msg_exe_main + 0xa1 (CCL_MSG)  

0x29862: __tmainCRTStartup + 0x10e (quartus_map)  

0x8363: BaseThreadInitThunk + 0x13 (KERNEL32)  

0x670d0: RtlUserThreadStart + 0x20 (ntdll)  

 

 

End-trace  

 

 

Executable: quartus_map 

Comment: 

None 

 

system information 

Platform: windows64 

OS name: Windows 10 

OS version: 10.0 

 

quartus prime information 

Address bits: 64 

Version: 16.1.0 

Build: 196 

Edition: Standard Edition 

----------------------------------------------------------------- 

I have found the code which causes this issue. But I don't know why the code causes the problem. Also, I don't know how to solve it. Here is the code: 

initial 

begin 

$readmemb("../data/file1.txt", rom1); 

$readmemb("../data/file2.txt", rom2); 

end 

It seems tha quartus doesn't allow me to initialize two ROMs in one verilog file. After I remove either one of the two $readmemb statement, quartus can synthesis successfully. 

I have also tried used two seperate initial blocks, each block contains one $readmemb. This doesn't solve the problem. 

I use the template provided by quartus to implement the two roms. Rom is inferred correctly.  

How do I solve this problem? I need to initialize multiple roms and rams in my project. 

Thank you! 

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Altera_Forum
Honored Contributor II
624 Views

You will need to raise a myrequest ticket to see what the problem is.

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