question about VHDL code

Altera_Forum · ‎03-04-2012

Hi guys,

I am wondering what circuit will be generated based on the following VHDL code by Quartus II synthesizer? Thanks.

/****VHDL code begins****/

entity con_0 is

port ( cout: out bit_vector(3 downto 0));

end con_0;

architecture con_0_arch of con_0 is

begin

cout<="0101";

end con_0_arch;

/****VHDL code ends****/

Altera_Forum · ‎03-04-2012

The same 'circuit' as the statement

cout<="0101";

i.e., it will generate cout with a static value.

If that static value goes nowhere, then the synthesis tool will delete it. If however cout is used, for example cout is tied to pins on the FPGA, then Quartus will keep the signal.

Use the RTL viewer to see what the 'circuit' looks like.

Cheers,

Dave

Altera_Forum · ‎03-04-2012

You can compile a design and check the result in RTL and postsynthesis netlist viewer.